ASRock X99 Extreme4 User Manual - Page 69

Write to Read Delay tWTR_L, Read to Precharge tRTP, Four Activate Window tFAW, CAS Write Latency

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X99 Extreme4 Write to Read Delay (tWTR_L) he number of clocks between the last valid write operation and the next read command to the same internal bank. Read to Precharge (tRTP) he number of clocks that are inserted between a read command to a row precharge command to the same rank. Four Activate Window (tFAW) he time window in which four activates are allowed the same rank. CAS Write Latency (tCWL) Conigure CAS Write Latency. tREFI Conigure refresh cycles at an average periodic interval. tCKE Conigure the period of time the DDR4 initiates a minimum of one refresh command internally once it enters Self-Refresh mode. tCCCD Conigure back to back CAS to CAS (i.e. READ to RAED or WRITE to WRITE) from same rank separation parameter. tCCCD_L Conigure back to back CAS to CAS (i.e. READ to RAED or WRITE to WRITE) from same rank separation parameter. tCCCD_WR_L Conigure back to back CAS to CAS (i.e. READ to RAED or WRITE to WRITE) from same rank separation parameter. tRWSR Conigure READ to WRITE same rank dead cycle Back to back READ to WRITE from same rank separation parameter. tRWDD Conigure Read to Write diferent DIMM dead cycle Back to back READ to WRITE from diferent DIMM separation parameter. 63 English

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63
English
X99 Extreme4
Write to Read Delay (tWTR_L)
He number of clocks between the last valid write operation and the next read command to
the same internal bank.
Read to Precharge (tRTP)
He number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
He time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Con±gure CAS Write Latency.
tREFI
Con±gure refresh cycles at an average periodic interval.
tCKE
Con±gure the period of time the DDR4 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
tCCCD
Con±gure back to back CAS to CAS (i.e. READ to RAED or WRITE to WRITE)
from same rank separation parameter.
tCCCD_L
Con±gure back to back CAS to CAS (i.e. READ to RAED or WRITE to WRITE)
from same rank separation parameter.
tCCCD_WR_L
Con±gure back to back CAS to CAS (i.e. READ to RAED or WRITE to WRITE)
from same rank separation parameter.
tRWSR
Con±gure READ to WRITE same rank dead cycle Back to back READ to WRITE
from same rank separation parameter.
tRWDD
Con±gure Read to Write diµerent DIMM dead cycle Back to back READ to WRITE
from diµerent DIMM separation parameter.