ASRock Z690 PG Velocita User Manual - Page 87
RAS to RAS Delay tRRD_S
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Z690 PG Velocita Refresh Cycle Time per Bank (tRFCpb) The number of clocks from a Refresh command (per bank) until the first Activate command to the same rank. RAS to RAS Delay (tRRD_L) The number of clocks between two rows activated in different banks of the same rank. RAS to RAS Delay (tRRD_S) The number of clocks between two rows activated in different banks of the same rank. Read to Precharge (tRTP) The number of clocks that are inserted between a read command to a row precharge command to the same rank. Four Activate Window (tFAW) The time window in which four activates are allowed the same rank. CAS Write Latency (tCWL) Configure CAS Write Latency. Third Timing tREFI Configure refresh cycles at an average periodic interval. tCKE Configure the period of time the DDR5 initiates a minimum of one refresh command internally once it enters Self-Refresh mode. Turn Around Timing Turn Around Timing Optimization Auto is enabled in general case. TAT Training Value tRDRD_sg Configure between module read to read delay. 79 English