ASRock Z690 PG Velocita User Manual - Page 90

Initial RTL MC0 C1 A1/A2

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tWRWR_sg Configure between module write to write delay. tWRWR_dg Configure between module write to write delay. tWRWR_dr Configure between module write to write delay. tWRWR_dd Configure between module write to write delay. Round Trip Timing Round Trip Timing Optimization Auto is enabled in general case. Round Trip Level Configure round trip level. Initial RTL (MC0 C0 A1/A2) Configure round trip latency initial value. Initial RTL (MC0 C1 A1/A2) Configure round trip latency initial value. Initial RTL (MC1 C0 B1/B2) Configure round trip latency initial value. Initial RTL (MC1 C1 B1/B2) Configure round trip latency initial value. RTL (MC0 C0 A1/A2) Configure round trip latency value. ODT Setting Dimm ODT Training ODT values will be optimized by Dimm On-Die Termination Training. ODT WR (A1) Configure the memory on die termination resistors' WR for channel A1. 82 English

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English
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tWRWR_sg
Configure between module write to write delay.
tWRWR_dg
Configure between module write to write delay.
tWRWR_dr
Configure between module write to write delay.
tWRWR_dd
Configure between module write to write delay.
Round Trip Timing
Round Trip Timing Optimization
Auto is enabled in general case.
Round Trip Level
Configure round trip level.
Initial RTL (MC0 C0 A1/A2)
Configure round trip latency initial value.
Initial RTL (MC0 C1 A1/A2)
Configure round trip latency initial value.
Initial RTL (MC1 C0 B1/B2)
Configure round trip latency initial value.
Initial RTL (MC1 C1 B1/B2)
Configure round trip latency initial value.
RTL (MC0 C0 A1/A2)
Configure round trip latency value.
ODT Setting
Dimm ODT Training
ODT values will be optimized by Dimm On-Die Termination Training.
ODT WR (A1)
Configure the memory on die termination resistors' WR for channel A1.