Biostar 945GC MICRO 775 Setup Manual - Page 68
SLP S4# Assertion Width, System BIOS Cacheable, Video BIOS Cacheable, Memory Hole At 15M-16M
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945GC-M7 SE / 945GC Micro 775 SLP S4# Assertion Width This item sets the minimum assertion width of the SLP-S4# signal to guarantee the DRAM has been safely power-cycled. The Choices: 4 to 5 Sec. (default), 3 to 4 Sec., 2 to 3 Sec., 1 to 2 Sec. System BIOS Cacheable Selecting Enabled allows you caching of the system BIOS ROM at F0000h~FFFFFh, resulting a better system performance. However, if any program writes to this memory area, a system error may result. The Choices: Enabled (default), Disabled. Video BIOS Cacheable Select Enabled allows caching of the video BIOS, resulting a better system performance. However, if any program writes to this memory area, a system error may result. The Choices: Disabled (default), Enabled. Memory Hole At 15M-16M You can reserve this area of system memory for ISA adapter ROM. When this area is reserved it cannot be cached. The user information of peripherals that need to use this area of system memory usually discussed their memory requirements. The Choices: Disabled (default), Enabled. 16