Biostar M6VLA M6VLA user's manual - Page 6

Motherboard Description - drivers

Page 6 highlights

Chapter 1 Motherboard Description 1. Motherboard Description 1.1 Features 1.1.1 Hardware CPU − Supports the CeleronTM processor (PPGA) and the Pentium® !!! Micro-Processor for high-end workstations and servers. − CPU Socket 370. − Runs at 66/100/133 Mhz Front Side Bus frequency. DRAM Memory − Supports two 8/16/32/64/128/256 MB DIMM module sockets. − Supports Synchronous DRAM (3.3V). − Supports a maximum memory size of 512 MB with SDRAM. − 133Mhz Bus frequency. Internal Accelerated Graphics Port (AGP) Controller − AGP v1.0 compliant. − Pipelined split-transaction long-burst transfers up to 533 MB/sec. − Eight level read request queue. − Four level posted-write request queue. − Thirty-two level (quadwords) read data FIFO (128 bytes). − Sixteen level (quadwords) write data FIFO( 64 bytes). − Intelligent request reordering for maximum AGP bus utilization. − Supports Flush /Fence commands. − Graphics Address Relocation Table (GART). − One level TLB structure. − Sixteen entry fully associative page table. − LRU replacement scheme. − Independent GART lookup control for host /AGP /PCI master accesses. − Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport driver support. 1-2

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Chapter 1
Motherboard Description
1-2
1. Motherboard Description
1.1 Features
1.1.1 Hardware
CPU
Supports the Celeron
TM
processor (PPGA) and the Pentium
®
!!!
Micro-Processor for high-end workstations and servers.
CPU Socket 370.
Runs at 66/100/133 Mhz Front Side Bus frequency.
DRAM Memory
Supports two 8/16/32/64/128/256 MB DIMM module sockets.
Supports Synchronous DRAM (3.3V).
Supports a maximum memory size of 512 MB with SDRAM.
133Mhz Bus frequency.
Internal Accelerated Graphics Port (AGP) Controller
AGP v1.0 compliant.
Pipelined split-transaction long-burst transfers up to 533 MB/sec.
Eight level read request queue.
Four level posted-write request queue.
Thirty-two level (quadwords) read data FIFO (128 bytes).
Sixteen level (quadwords) write data FIFO( 64 bytes).
Intelligent request reordering for maximum AGP bus utilization.
Supports Flush /Fence commands.
Graphics Address Relocation Table (GART).
One level TLB structure.
Sixteen entry fully associative page table.
LRU replacement scheme.
Independent GART lookup control for host /AGP /PCI master
accesses.
Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport
driver support.