Canon BJ-10E Service Manual - Page 98

TC24SC090AF

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Part 3: Technical Reference b) Printer controller The printer controller (Toshiba TC24SC090AF) contains the interface controller, DRAM controller, print head controller, and address decoder. The independent 20 MHz clock input to the printer controller time the interface and DRAM bus. The bus timing with the CPU is determined by 2.5 MHz CLKO input from the CPU. • Interface controller The Centronics type interface controller receives 8-bit parallel data from the computer in synchrony with the data strobe pulse by BUSY/-ACK handshaking. This controller also controls other interface signals. The data received via the interface is stored in the DRAM receive buffer (usually, 37 Kbytes; 3 Kbytes when font is downloaded) and analyzed by the MPU. When printer initialize signal "-INIT. enters the printer controller and CPU via the interface, the printer controller immediately outputs the BUSY status, and the CPU prints the data in the print buffer and initializes the printer. LOOK See the User's Manual for details about interface timing and signals. • DRAM controller The DRAM controller controls the independent 8-bit address/data buses and read/write, RAS/CAS, and refresh of two 64K x 4-bit DRAMs at the upper part (4 bits) and lower part (4 bits). • Print head controller The print head controller converts the bit map print data read from the DRAM print buffer to COM and SEG signals that control 8 x 8 matrix printing and controls the heater plates of the 64 bubble jet nozzles of the BJ cartridge with the 3 kHz drive frequency. LOOK For details about the print signals, see the BJ cartridge section. • Address decoder When the CPU address bus addresses the ROM or PPI, the address decoder outputs a chip select signal to each component. When the CPU addresses the DRAM to analyze data in the receive buffer and read/write a work area, the address decoder outputs a -WAIT signal to the CPU to synchronize the CPU and DRAM timing, and reduce the CPU read/write cycle to half speed. 3-30

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Part
3:
Technical
Reference
b)
Printer
controller
The
printer
controller
(Toshiba
TC24SC090AF)
contains
the
interface
controller,
DRAM
controller,
print
head
controller,
and
address
decoder.
The
independent
20
MHz
clock
input
to
the
printer
controller
time
the
interface
and
DRAM
bus.
The
bus
timing
with
the
CPU
is
determined
by
2.5
MHz
CLKO
input
from
the
CPU.
•
Interface
controller
The
Centronics
type
interface
controller
receives
8
-bit
parallel
data
from
the
computer
in
synchrony
with
the
data
strobe
pulse
by
BUSY/-ACK
handshaking.
This
controller
also
controls
other
interface
signals.
The
data
received
via
the
interface
is
stored
in
the
DRAM
receive
buffer
(usually,
37
Kbytes;
3
Kbytes
when
font
is
downloaded)
and
analyzed
by
the
MPU.
When
printer
initialize
signal
"-INIT
.
enters
the
printer
controller
and
CPU
via
the
interface,
the
printer
controller
immediately
outputs
the
BUSY
status,
and
the
CPU
prints
the
data
in
the
print
buffer
and
initializes
the
printer.
LOOK
See
the
User's
Manual
for
details
about
interface
timing
and
signals.
•
DRAM
controller
The
DRAM
controller
controls
the
independent
8
-bit
address/data
buses
and
read/write,
RAS/CAS,
and
refresh
of
two
64K
x
4
-bit
DRAMs
at
the
upper
part
(4
bits)
and
lower
part
(4
bits).
•
Print
head
controller
The
print
head
controller
converts
the
bit
map
print
data
read
from
the
DRAM
print
buffer
to
COM
and
SEG
signals
that
control
8
x
8
matrix
printing
and
controls
the
heater
plates
of
the
64
bubble
jet
nozzles
of
the
BJ
cartridge
with
the
3
kHz
drive
frequency.
LOOK
For
details
about
the
print
signals,
see
the
BJ
cartridge
section.
•
Address
decoder
When
the
CPU
address
bus
addresses
the
ROM
or
PPI,
the
address
decoder
outputs
a
chip
select
signal
to
each
component.
When
the
CPU
addresses
the
DRAM
to
analyze
data
in
the
receive
buffer
and
read/write
a
work
area,
the
address
decoder
outputs
a
-WAIT
signal
to
the
CPU
to
synchronize
the
CPU
and
DRAM
timing,
and
reduce
the
CPU
read/write
cycle
to
half
speed.
3-30