HP DL740 HP F8 Architecture Technology Brief - Page 1

HP DL740 - ProLiant - 4 GB RAM Manual

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HP Industry Standard Servers April 2003 Technology Brief TC0304013TB Table of Contents HP F8 Architecture Abstract...2 Introduction ...2 Need for F8 Architecture 2 Overview of F8 Chipset 4 Hot-Plug RAID Memory 5 Memory Configuration...5 RAID Memory Striping ...5 Hot-Plug Memory Capabilities 6 Benefits of Data Protection With RAID 7 Error Detection and Correction 7 Architectural Differences From Storage Subsystem RAID 8 F8 Crossbar Switch 8 Buffer Design...8 Multiport Design ...9 Cache Coherency Filter ...9 Optimizing Cross-bus Traffic 10 I/O Subsystem...11 PCI Mode ...11 PCI-X Mode ...11 Xeon MP Processor Subsystem 12 Hyper-Threading Technology 12 Frequency and Full-Speed Cache 13 Processor and I/O Bus Design 13 SIMD Instructions ...13 Out-of-order Execution ...13 Branch Prediction ...13 Conclusion...14 Feedback...14 1

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HP F8 Architecture
Table of Contents
April 2003
HP Industry
Standard Servers
Technology Brief
TC0304013TB
Abstract
....................................................................................................................
2
Introduction
..............................................................................................................
2
Need for F8 Architecture
...........................................................................................
2
Overview of F8 Chipset
.............................................................................................
4
Hot-Plug RAID Memory
.............................................................................................
5
Memory Configuration
.......................................................................................................
5
RAID Memory Striping
.......................................................................................................
5
Hot-Plug Memory Capabilities
............................................................................................
6
Benefits of Data Protection With RAID
................................................................................
7
Error Detection and Correction
...........................................................................................
7
Architectural Differences From Storage Subsystem RAID
......................................................
8
F8 Crossbar Switch
...................................................................................................
8
Buffer Design
.....................................................................................................................
8
Multiport Design
................................................................................................................
9
Cache Coherency Filter
......................................................................................................
9
Optimizing
Cross-bus Traffic
...........................................................................................
10
I/O Subsystem
........................................................................................................
11
PCI Mode
........................................................................................................................
11
PCI-X Mode
.....................................................................................................................
11
Xeon MP Processor Subsystem
................................................................................
12
Hyper-Threading Technology
...........................................................................................
12
Frequency and Full-Speed Cache
.....................................................................................
13
Processor and I/O Bus Design
..........................................................................................
13
SIMD Instructions
.............................................................................................................
13
Out-of-order Execution
....................................................................................................
13
Branch Prediction
............................................................................................................
13
Conclusion
..............................................................................................................
14
Feedback
................................................................................................................
14