HP DL740 HP F8 Architecture Technology Brief - Page 2

HP F8 Architecture Abstract Introduction Need for F8 Architecture HP has developed an 8-way multiprocessing architecture that will meet or exceed the greatly increased bandwidth demands of high-end peripherals and the Intel Xeon MP processors. The HP F8 chipset provides key functionality, such as Hot Plug RAID Memory, that was previously unavailable within industry-standard servers. Like redundant array of independent disk technology used in storage subsystems, Hot Plug RAID Memory uses a redundant array of industry-standard DIMMs (RAID) to provide both fault tolerance and the ability to hot replace and hot add memory while the server is operating. The F8 chipset uses a multiport, nonblocking crossbar switch to optimize efficiency and allow simultaneous access to memory, processor, and I/O subsystems. The F8 chipset supports multiple PCI-X bridges and incorporates the HP embedded PCI Hot Plug controller for high availability in the I/O subsystem. The balanced architecture of the F8 chipset will deliver superior performance for the most demanding applications, whether they are memory intensive, I/O intensive, or processor intensive. HP has leveraged experience Compaq gained from the development1 and use of the Profusion 8-way architecture to design a new 8-way multiprocessing architecture with even higher performance: the F8 architecture. This new architecture is based on the Intel® Xeon MP processors. It is designed to deliver high bandwidth and performance for I/O, processor, and memory requirements in 2003 and beyond. The F8 architecture includes HP Hot-Plug RAID Memory―a new technology within HP Advanced Memory Protection, designed for achieving high availability, scalability, and fault tolerance within the memory subsystem. Hot-Plug RAID Memory uses a redundant array of industry-standard DIMMs2 (RAID) to provide availability and fault tolerance in the memory subsystem, much as redundant array of independent disk (RAID) technology provides availability and fault tolerance in storage subsystems. HP designed the F8 architecture with increased memory bandwidth, a nonblocking crossbar switch that improves bus efficiency, and PCI Hot-Plug and PCI-X capabilities in the I/O subsystem. Industry-standard servers using this architecture will vary in implementation. This technology brief describes the capabilities of the F8 architecture. For the purposes of this brief, the new bus architecture for the Intel Xeon MP is referred to as the Xeon MP processor bus. In 2003, high-end Intel 32-bit processors will operate at speeds greater than 2 GHz and support a bus with four times the bandwidth of the P6 processor bus. (P6 is the family name for Intel processors starting with the Intel Pentium Pro and continuing through the Pentium III Xeon processor.) Peripherals are moving to high-speed interconnects such as Gigabit Ethernet and Ultra320 SCSI, which operate at bandwidths of 125 megabytes per second (MB/s) and 320 MB/s, respectively. Clearly, servers will need high processor-to-memory bandwidth as well as high I/O-to-memory bandwidth. Achieving optimum performance requires a balanced server architecture to ensure that every subsystem-processor, I/O, and memory-has adequate bandwidth. Compaq worked with Corollary to develop the highly successful, balanced architecture in the Profusion 8-way chipset. HP has used that experience to design its own 8-way chipset that maximizes bandwidth and performance in all subsystems. 1 The record-setting Profusion architecture was co-developed by Compaq and Corollary. 2 DIMMs is an acronym for dual inline memory module. 2