HP Integrity rx1600 Operation and Maintenance - HP Integrity rx1600 - Page 188

System Information System Board • Flash memory • Non-volatile memory • Scratch RAM • Real Time Clock • UARTs • External Registers • Firmware read/writable registers • Two general purpose 32-bit registers • Semaphore registers • Monarch selection registers • Test and Reset register • Reset and INIT generation Dual Serial Controller The dual serial controller is a dual universal asynchronous receiver and transmitter (DUART). This chip provides enhanced UART functions with 16-byte FIFOs, a modem control interface. Registers on this chip provide onboard error indications and operation status. An internal loopback capability provides onboard diagnostics. Features include: • Data rates up to 115.2kbps • 16550A fully compatible controller • A 16-byte transmit FIFO to reduce the bandwidth requirement of the external CPU • A 16-byte receive FIFO with four selectable interrupt trigger levels and error flags to reduce the bandwidth requirement of the external CPU • UART control that provides independent transmit and receive • Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD, and software controllable line break) • Programmable character lengths (5, 6, 7, 8) with Even, Odd or No Parity • A status report register Field Programmable Gate Array The field programmable gate array (FPGA) provides ACPI and low pin count (LPC) support for HP Intel Itanium 2 platforms based on HP chipsets. This controller is connected to the PDH bus and provides these features: • ACPI 2.0 interface • LPC bus interface to support BMC • Decoding logic for PDH devices 188 Appendix A