HP rp7440 User Service Guide, Fourth Edition - HP Integrity rx7640 and HP 9000 - Page 26
Memory Subsystem, CPU Locations on Cell Board
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Figure 1-8 CPU Locations on Cell Board Socket 2 Socket 3 Cell Controller Socket 1 Socket 0 Memory Subsystem Figure 1-9 shows a simplified view of the memory subsystem. It consists of two independent access paths, each path having its own address bus, control bus, data bus, and DIMMs . Address and control signals are fanned out through register ports to the synchronous dynamic random access memory (SDRAM) on the DIMMs. The memory subsystem comprises four independent quadrants. Each quadrant has its own memory data bus connected from the cell controller to the two buffers for the memory quadrant. Each quadrant also has two memory control buses; one for each buffer. 26 HP Integrity rx7640 Server and HP 9000 rp7440 Server Overview
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Figure 1-8 CPU Locations on Cell Board
Socket 2
Socket 3
Socket 1
Socket 0
Cell
Controller
Memory Subsystem
Figure 1-9
shows a simplified view of the memory subsystem. It consists of two independent
access paths, each path having its own address bus, control bus, data bus, and DIMMs . Address
and control signals are fanned out through register ports to the synchronous dynamic random
access memory (SDRAM) on the DIMMs.
The memory subsystem comprises four independent quadrants. Each quadrant has its own
memory data bus connected from the cell controller to the two buffers for the memory quadrant.
Each quadrant also has two memory control buses; one for each buffer.
26
HP Integrity rx7640 Server and HP 9000 rp7440 Server Overview