HP rp8440 Site Preparation Guide, Fourth Edition - HP Integrity rx8640, HP 900 - Page 20
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The memory subsystem comprises four independent quadrants. Each quadrant has its own memory data bus connected from the cell controller to the two buffers for the memory quadrant. Each quadrant also has two memory control buses: one for each buffer. Figure 1-8 Memory Subsystem DIMM DIMM Address/ Buffer Controller Buffer Buffer PDH Riser Board DIMM DIMM Address/ Buffer Controller Buffer Buffer QUAD 1 QUAD 3 DIMM DIMM DIMM DIMM To Quad 2 Address/Controller Buffers To Quad 3 Address/Controller Buffers To Quad 1 Address/Controller Buffers To Quad 0 Address/Controller Buffers QUAD 0 QUAD 2 DIMM DIMM Address/ Buffer Controller Buffer Buffer DIMM DIMM DIMM DIMM Address/ Buffer Controller Buffer Buffer DIMM DIMM Front Side Bus 1 CPU 2 CPU 3 Cell Controller Front Side Bus 0 CPU 1 CPU 0 DIMMs The memory DIMMs used by the server are custom designed by HP. Each DIMM contains DDR-II SDRAM memory that operates at 533 MT/s. Industry standard modules do not support the high availability and shared memory features of the server. Therefore, industry standard DIMM modules are not supported. The server supports DIMMs with densities of 1, 2, 4, and 8 GB. Table 1-2 lists each supported DIMM size, the resulting total server capacity, and the memory component density. Each DIMM is connected to two buffer chips on the cell board. Table 1-2 DIMM Sizes Supported DIMM Size 1 GB 2 GB 4 GB 8 GB Total Capacity 64 GB 128 GB 256 GB 512 GB Memory Component Density 256 Mb 512 Mb 1024 Mb 2048 Mb 20 HP Integrity rx8640 and HP 9000 rp8440 Server Overview