Hitachi DK23FB-60 Owners Manual - Page 97
Interface Signal Timing, 4.1 Data Transfer Timing
UPC - 706569123807
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6.4 Interface Signal Timing 6.4.1 Data Transfer Timing Figures 6-4, 6-5, and 6-7 show the timing for asserting interface signals for transferring 16-bit and 8-bit data. Figure 6-4 PIO Data Transfer Timing(Mode 4) t0 Addr Valid *1 t1 t2 t9 DIOR-/DIOW- t2i t8 Write Data Valid *2 Read Data Valid *2 t7 IOCS16- t3 t4 t5 t6 t6Z *1 Device Address consists of signals CS0-, CS1-, and DA2-0 *2 Data consists of DD0-15(16 bit) or DD0-7(8 bit) SYMBOL Description MIN(ns) t0 Cycle Time 120 t1 Address Valid to DIOR-/DIOW- Setup 25 t2 DIOR-/DIOW- Pulse Width 70 t2i DIOR-/DIOW- Recovery 25 t3 DIOW- Data Setup 20 t4 DIOW- Data Hold 10 t5 DIOR- Data Setup 20 t6 DIOR- Data Hold 5 t6Z DIOR- Data tristate t7 Addr Valid To IOCS16- Assertion(MAX) t8 Addr Valid To IOCS16- Negation (MAX) t9 DIOR-/DIOW- to Address Valid Hold 10 MAX(ns) 30 40 30 K6610007 Rev.5 02.14.'03 - 97 -