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Fixed I/O Map

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Intel Desktop Board D946GZAB Technical Product Specification 2.3 Fixed I/O Map Table 11. I/O Map Address (hex) 0000 - 00FF Size 256 bytes 01F0 - 01F7 0228 - 022F (Note 1) 0278 - 027F (Note 1) 02E8 - 02EF (Note 1) 02F8 - 02FF (Note 1) 0378 - 037F 03B0 - 03BB 03C0 - 03DF 03E8 - 03EF 03F0 - 03F5 03F4 - 03F7 03F8 - 03FF 04D0 - 04D1 LPTn + 400 0CF8 - 0CFB (Note 2) 0CF9 (Note 3) 0CFC - 0CFF FFA0 - FFA7 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 12 bytes 32 bytes 8 bytes 6 bytes 4 bytes 8 bytes 2 bytes 8 bytes 4 bytes 1 byte 4 bytes 8 bytes Description Used by the Desktop Board D946GZAB. Refer to the ICH7 data sheet for dynamic addressing information. Primary Parallel ATE IDE channel command block LPT3 LPT2 COM4 COM2 LPT1 Intel 82946GZ GMCH Intel 82946GZ GMCH COM3 Diskette channel Primary Parallel ATA IDE channel control block COM1 Edge/level triggered PIC ECP port, LPTn base address + 400h PCI configuration address register Reset control register PCI configuration data register Primary Parallel ATA IDE bus master registers Notes: 1. Default, but can be changed to another address range 2. Dword access only 3. Byte access only NOTE Some additional I/O addresses are not available due to ICH7 address aliasing. The ICH7 data sheet provides more information on address aliasing. For information about Obtaining the ICH7 data sheet Refer to Section 1.2 on page 15 42

Section	Page
Intel® Desktop Board D946GZAB Technical Product Specification	1
Revision History / Disclaimer	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Contents	5
1 Product Description	9
1.1 Overview	10
1.1.1 Feature Summary	10
1.1.2 Board Layout	12
1.1.3 Block Diagram	14
1.2 Online Support	15
1.3 Processor	15
1.4 System Memory	16
1.4.1 Memory Configurations	18
1.5 Intel® 946GZ Express Chipset	21
1.5.1 Intel 946GZ Graphics Subsystem	21
1.5.2 USB	23
1.5.3 Serial ATA Interfaces	24
1.5.4 Parallel IDE Interface	25
1.5.5 Real-Time Clock, CMOS SRAM, and Battery	25
1.6 Legacy I/O Controller	26
1.6.1 Serial Port	26
1.6.2 Parallel Port	26
1.6.3 Diskette Drive Controller	26
1.6.4 Keyboard and Mouse Interface	26
1.7 Audio Subsystem	27
1.7.1 Audio Subsystem Software	28
1.7.2 Audio Connectors and Headers	28
1.8 LAN Subsystem	29
1.8.1 Intel® 82562GX PLC Device	29
1.8.2 LAN Subsystem Software	29
1.8.3 RJ-45 LAN Connector with Integrated LEDs	29
1.9 Hardware Management Subsystem	30
1.9.1 Hardware Monitoring and Fan Control	30
1.9.2 Fan Monitoring	30
1.9.3 Chassis Intrusion and Detection	30
1.9.4 Thermal Monitoring	31
1.10 Power Management	32
1.10.1 ACPI	32
1.10.2 Hardware Support	34
2 Technical Reference	39
2.1 Memory Map	39
2.1.1 Addressable Memory	39
2.2 DMA Channels	41
2.3 Fixed I/O Map	42
2.4 PCI Configuration Space Map	43
2.5 Interrupts	44
2.6 PCI Interrupt Routing Map	45
2.7 Connectors and Headers	46
2.7.1 Back Panel Connectors	47
2.7.2 Component-side Connectors and Headers	48
2.8 Jumper Block	56
2.9 Mechanical Considerations	57
2.9.1 Form Factor	57
2.9.2 I/O Shield	58
2.10 Electrical Considerations	59
2.10.1 DC Loading	59
2.10.2 Fan Header Current Capability	59
2.10.3 Add-in Board Considerations	60
2.10.4 Power Supply Considerations	60
2.11 Thermal Considerations	61
2.12 Reliability	63
2.13 Environmental	63
3 Overview of BIOS Features	65
3.1 Introduction	65
3.2 BIOS Flash Memory Organization	66
3.3 Resource Configuration	66
3.3.1 PCI Autoconfiguration	66
3.3.2 PCI IDE Support	67
3.4 System Management BIOS (SMBIOS)	67
3.5 Legacy USB Support	68
3.6 BIOS Updates	68
3.6.1 Language Support	69
3.6.2 Custom Splash Screen	69
3.7 BIOS Recovery	69
3.8 Boot Options	70
3.8.1 CD-ROM Boot	70
3.8.2 Network Boot	70
3.8.3 Booting Without Attached Devices	70
3.8.4 Changing the Default Boot Device During POST	70
3.9 Adjusting Boot Speed	71
3.9.1 Peripheral Selection and Configuration	71
3.9.2 BIOS Boot Optimizations	71
3.10 BIOS Security Features	72
4 Error Messages and Beep Codes	73
4.1 Speaker	73
4.2 BIOS Beep Codes	73
4.3 BIOS Error Messages	73
4.4 Port 80h POST Codes	74
5 Regulatory Compliance and Battery Disposal Information	79
5.1 Regulatory Compliance	79
5.1.1 Safety Regulations	79
5.1.2 European Union Declaration of Conformity Statement	79
5.1.3 Product Ecology Statements	82
5.1.4 EMC Regulations	85
5.1.5 Product Certification Markings (Board Level)	86

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Intel Desktop Board D946GZAB Technical Product Specification

2.3

Fixed I/O Map

Table 11. I/O Map

Address (hex)

Size

Description

0000 - 00FF

256 bytes

Used by the Desktop Board D946GZAB.

Refer to the ICH7

data sheet for dynamic addressing information.

01F0 - 01F7

8 bytes

Primary Parallel ATE IDE channel command block

0228 - 022F

(Note 1)

8 bytes

LPT3

0278 - 027F

(Note 1)

8 bytes

LPT2

02E8 - 02EF

(Note 1)

8 bytes

COM4

02F8 - 02FF

(Note 1)

8 bytes

COM2

0378 - 037F

8 bytes

LPT1

03B0 - 03BB

12 bytes

Intel 82946GZ GMCH

03C0 - 03DF

32 bytes

Intel 82946GZ GMCH

03E8 - 03EF

8 bytes

COM3

03F0 - 03F5

6 bytes

Diskette channel

03F4 - 03F7

4 bytes

Primary Parallel ATA IDE channel control block

03F8 - 03FF

8 bytes

COM1

04D0 - 04D1

2 bytes

Edge/level triggered PIC

LPTn + 400

8 bytes

ECP port, LPTn base address + 400h

0CF8 - 0CFB

(Note 2)

4 bytes

PCI configuration address register

0CF9

(Note 3)

1 byte

Reset control register

0CFC - 0CFF

4 bytes

PCI configuration data register

FFA0 - FFA7

8 bytes

Primary Parallel ATA IDE bus master registers

Notes:

Default, but can be changed to another address range

Dword access only

Byte access only

NOTE

Some additional I/O addresses are not available due to ICH7 address aliasing.

The

ICH7 data sheet provides more information on address aliasing.

For information about

Refer to

Obtaining the ICH7 data sheet

Section 1.2 on page 15