Intel BLKD946GZABL Product Specification - Page 7

Regulatory Compliance and Battery Disposal Information, s, Tables

Get Intel BLKD946GZABL PDF manuals and user guides View all Intel BLKD946GZABL manuals
Add to My Manuals
Save this manual to your list of manuals

Page 7 highlights

Contents 5 Regulatory Compliance and Battery Disposal Information 5.1 Regulatory Compliance 79 5.1.1 Safety Regulations 79 5.1.2 European Union Declaration of Conformity Statement 79 5.1.3 Product Ecology Statements 82 5.1.4 EMC Regulations 85 5.1.5 Product Certification Markings (Board Level 86 5.2 Battery Disposal Information 87 Figures 1. Major Board Components 12 2. Block Diagram 14 3. Memory Channel and DIMM Configuration 18 4. Dual Channel (Interleaved) Mode Configuration with Two DIMMs 19 5. Single Channel (Asymmetric) Mode Configuration with One DIMM .......... 20 6. Single Channel (Asymmetric) Mode Configuration with Two DIMMs ......... 20 7. 6-Channel (5.1) Audio Subsystem Block Diagram 27 8. Front/Back Panel Audio Connector Options 28 9. LAN Connector LED Locations 29 10. Thermal Sensors and Fan Headers 31 11. Location of the Standby Power Indicator LED 37 12. Detailed System Memory Address Map 40 13. Back Panel Connectors 47 14. Component-side Connectors and Headers 48 15. Connection Diagram for Front Panel Header 53 16. Connection Diagram for Front Panel USB Headers 55 17. Location of the Jumper Block 56 18. Board Dimensions 57 19. I/O Shield Dimensions 58 20. Localized High Temperature Zones 62 Tables 1. Feature Summary 10 2. Board Components Shown in Figure 1 13 3. Supported Memory Configurations 16 4. Memory Operating Frequencies 17 5. LAN Connector LED States 30 6. Effects of Pressing the Power Switch 32 7. Power States and Targeted System Power 33 8. Wake-up Devices and Events 34 9. System Memory Map 41 10. DMA Channels 41 11. I/O Map 42 12. PCI Configuration Space Map 43 13. Interrupts 44 vii

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
Contents
vii
5
Regulatory Compliance and Battery Disposal Information
5.1
Regulatory Compliance
.....................................................................
79
5.1.1
Safety Regulations
................................................................
79
5.1.2
European Union Declaration of Conformity Statement
................
79
5.1.3
Product Ecology Statements
...................................................
82
5.1.4
EMC Regulations
..................................................................
85
5.1.5
Product Certification Markings (Board Level)
.............................
86
5.2
Battery Disposal Information
.............................................................
87
Figures
1.
Major Board Components
..................................................................
12
2.
Block Diagram
................................................................................
14
3.
Memory Channel and DIMM Configuration
...........................................
18
4.
Dual Channel (Interleaved) Mode Configuration with Two DIMMs
............
19
5.
Single Channel (Asymmetric) Mode Configuration with One DIMM
..........
20
6.
Single Channel (Asymmetric) Mode Configuration with Two DIMMs
.........
20
7.
6-Channel (5.1) Audio Subsystem Block Diagram
.................................
27
8.
Front/Back Panel Audio Connector Options
..........................................
28
9.
LAN Connector LED Locations
............................................................
29
10. Thermal Sensors and Fan Headers
.....................................................
31
11. Location of the Standby Power Indicator LED
.......................................
37
12. Detailed System Memory Address Map
...............................................
40
13. Back Panel Connectors
.....................................................................
47
14. Component-side Connectors and Headers
...........................................
48
15. Connection Diagram for Front Panel Header
........................................
53
16. Connection Diagram for Front Panel USB Headers
................................
55
17. Location of the Jumper Block
.............................................................
56
18. Board Dimensions
...........................................................................
57
19. I/O Shield Dimensions
......................................................................
58
20. Localized High Temperature Zones
.....................................................
62
Tables
1.
Feature Summary
............................................................................
10
2.
Board Components Shown in Figure 1
................................................
13
3.
Supported Memory Configurations
.....................................................
16
4.
Memory Operating Frequencies
.........................................................
17
5.
LAN Connector LED States
................................................................
30
6.
Effects of Pressing the Power Switch
..................................................
32
7.
Power States and Targeted System Power
...........................................
33
8.
Wake-up Devices and Events
............................................................
34
9.
System Memory Map
.......................................................................
41
10.
DMA Channels
.................................................................................
41
11.
I/O Map
.........................................................................................
42
12.
PCI Configuration Space Map
............................................................
43
13.
Interrupts
......................................................................................
44