Intel BOXD865GLCL Product Specification - Page 36

Dynamic Video Memory Technology DVMT, 8.1.4, Zone Rendering Technology ZRT, 8.1.5, Rapid

Page 36 highlights

Intel Desktop Board D865GBF/D865GLC Technical Product Specification 1.8.1.3 Dynamic Video Memory Technology (DVMT) DVMT enables enhanced graphics and memory performance through Direct AGP, and highly efficient memory utilization. DVMT ensures the most efficient use of available system memory for maximum 2-D/3-D graphics performance. Up to 64 MB of system memory can be allocated to DVMT on systems that have 256 MB or more of total system memory installed. Up to 32 MB can be allocated to DVMT on systems that have 128 MB but less than 256 MB of total installed system memory. Up to 8 MB can be allocated to DVMT when less than 128 MB of system memory is installed. DVMT returns system memory back to the operating system when the additional system memory is no longer required by the graphics subsystem. DVMT will always use a minimal fixed portion of system physical memory (as set in the BIOS Setup program) for compatibility with legacy applications. An example of this would be when using VGA graphics under DOS. Once loaded, the operating system and graphics drivers allocate additional system memory to the graphics buffer as needed for performing graphics functions. ✏ NOTE The use of DVMT requires operating system driver support. 1.8.1.4 Zone Rendering Technology (ZRT) The Intel Extreme Graphics 2 Controller supports Zone Rendering Technology (ZRT). ZRT is a process by which the screen is divided into several zones. Each zone is completely cached and rendered on chip before being written to the frame buffer. The benefits of ZRT include the following: • Increased memory efficiency via better localization of data • Increased on-chip processing speed due to decreased wait time for data • Increased effective pixel fill rates • Increased headroom for larger resolution and color depth • Reduced power as a result of decreased memory bandwidth • Reduction in depth and color bandwidth associated with conventional rendering 1.8.1.5 Rapid Pixel and Text Rendering (RPTR) The Rapid Pixel and Text Rendering Engine (RPTR) architecture utilizes special pipelines that allow 2D and 3D operations to overlap. By providing 8X compression, the RPTR engine reduces the memory bandwidth required to read texture memory, and reduces the amount of memory required for texture storage. A dedicated, non-blocking, multi-tier cache is provided for textures, colors, Z and vertex rendering. With single-pass, quad texture support, the drivers can submit up to four textures that pass to the graphics engine concurrently. The graphics core can switch between 2D and 3D operations without having to complete all operations of the same mode, which minimizes the overhead time required in switching between modes. A 2D Block Level Transfer (BLT) in the RPTR engine is extended to 256-bit, which supports fast blitter fill rate. This enables the blitter sequence of the same addresses to access the cache and offloads the memory bandwidth required to support blitter fill rate. Then the cache is emptied automatically when the sequence of operations are complete. 36

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Intel Desktop Board D865GBF/D865GLC Technical Product Specification
36
1.8.1.3
Dynamic Video Memory Technology (DVMT)
DVMT enables enhanced graphics and memory performance through Direct AGP, and highly
efficient memory utilization.
DVMT ensures the most efficient use of available system memory
for maximum 2-D/3-D graphics performance.
Up to 64 MB of system memory can be allocated to
DVMT on systems that have 256 MB or more of total system memory installed.
Up to 32 MB can
be allocated to DVMT on systems that have 128 MB but less than 256 MB of total installed system
memory.
Up to 8 MB can be allocated to DVMT when less than 128 MB of system memory is
installed.
DVMT returns system memory back to the operating system when the additional system
memory is no longer required by the graphics subsystem.
DVMT will always use a minimal fixed portion of system physical memory (as set in the BIOS
Setup program) for compatibility with legacy applications.
An example of this would be when
using VGA graphics under DOS.
Once loaded, the operating system and graphics drivers allocate
additional system memory to the graphics buffer as needed for performing graphics functions.
NOTE
The use of DVMT requires operating system driver support.
1.8.1.4
Zone Rendering Technology (ZRT)
The Intel Extreme Graphics 2 Controller supports Zone Rendering Technology (ZRT).
ZRT is a
process by which the screen is divided into several zones.
Each zone is completely cached and
rendered on chip before being written to the frame buffer.
The benefits of ZRT include the
following:
Increased memory efficiency via better localization of data
Increased on-chip processing speed due to decreased wait time for data
Increased effective pixel fill rates
Increased headroom for larger resolution and color depth
Reduced power as a result of decreased memory bandwidth
Reduction in depth and color bandwidth associated with conventional rendering
1.8.1.5
Rapid Pixel and Text Rendering (RPTR)
The Rapid Pixel and Text Rendering Engine (RPTR) architecture utilizes special pipelines that
allow 2D and 3D operations to overlap.
By providing 8X compression, the RPTR engine reduces
the memory bandwidth required to read texture memory, and reduces the amount of memory
required for texture storage.
A dedicated, non-blocking, multi-tier cache is provided for textures, colors, Z and vertex
rendering.
With single-pass, quad texture support, the drivers can submit up to four textures that
pass to the graphics engine concurrently.
The graphics core can switch between 2D and 3D
operations without having to complete all operations of the same mode, which minimizes the
overhead time required in switching between modes.
A 2D Block Level Transfer (BLT) in the RPTR engine is extended to 256-bit, which supports fast
blitter fill rate.
This enables the blitter sequence of the same addresses to access the cache and
offloads the memory bandwidth required to support blitter fill rate.
Then the cache is emptied
automatically when the sequence of operations are complete.