Intel D845GLLY D845GL_Boards_TechProdSpec - Page 38

Fixed I/O Map

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Technical Product Specification for Intel Desktop Boards using the Intel 845GL Chipset 2.3 Fixed I/O Map Table 15. Fixed I/O Map Address (hex) 0000 - 00FF Size 256 bytes 0170 - 0177 01F0 - 01F7 0228 - 022F (Note 1) 0278 - 027F (Note 1) 02E8 - 02EF (Note 1) 02F8 - 02FF (Note 1) 0376 0378 - 037F 03B0 - 03BB 03C0 - 03DF 03E8 - 03EF 03F0 - 03F5 03F6 03F8 - 03FF 04D0 - 04D1 LPTn + 400 0CF8 - 0CFB (Note 2) 0CF9 (Note 3) 0CFC - 0CFF FFA0 - FFA7 FFA8 - FFAF 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 1 byte 8 bytes 12 bytes 32 bytes 8 bytes 6 bytes 1 byte 8 bytes 2 bytes 8 bytes 4 bytes 1 byte 4 bytes 8 bytes 8 bytes Description Used by the Desktop Board. Refer to the ICH4 data sheet for dynamic addressing information. Secondary IDE channel Primary IDE channel LPT3 LPT2 COM4/video (8514A) COM2 Secondary IDE channel command port LPT1 Intel 82845GL GMCH Intel 82845GL GMCH COM3 Diskette channel 1 Primary IDE channel command port COM1 Edge/level triggered PIC ECP port, LPTn base address + 400h PCI configuration address register Turbo and reset control register PCI configuration data register Primary bus master IDE registers Secondary bus master IDE registers Notes: 1. Default, but can be changed to another address range 2. Dword access only 3. Byte access only ✏ NOTE Some additional I/O addresses are not available due to ICH4 address aliassing. The ICH4 data sheet provides more information on address aliassing. For information about Obtaining the ICH4 data sheet Refer to Section 1.2 on page 12 38

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Technical Product Specification for Intel Desktop Boards using the Intel 845GL Chipset
38
2.3 Fixed I/O Map
Table 15.
Fixed I/O Map
Address (hex)
Size
Description
0000 - 00FF
256 bytes
Used by the Desktop Board.
Refer to the ICH4 data sheet
for dynamic addressing information.
0170 - 0177
8 bytes
Secondary IDE channel
01F0 - 01F7
8 bytes
Primary IDE channel
0228 - 022F (Note 1)
8 bytes
LPT3
0278 - 027F (Note 1)
8 bytes
LPT2
02E8 - 02EF (Note 1)
8 bytes
COM4/video (8514A)
02F8 - 02FF (Note 1)
8 bytes
COM2
0376
1 byte
Secondary IDE channel command port
0378 - 037F
8 bytes
LPT1
03B0 - 03BB
12 bytes
Intel 82845GL GMCH
03C0 - 03DF
32 bytes
Intel 82845GL GMCH
03E8 - 03EF
8 bytes
COM3
03F0 - 03F5
6 bytes
Diskette channel 1
03F6
1 byte
Primary IDE channel command port
03F8 - 03FF
8 bytes
COM1
04D0 - 04D1
2 bytes
Edge/level triggered PIC
LPTn + 400
8 bytes
ECP port, LPTn base address + 400h
0CF8 - 0CFB (Note 2)
4 bytes
PCI configuration address register
0CF9 (Note 3)
1 byte
Turbo and reset control register
0CFC - 0CFF
4 bytes
PCI configuration data register
FFA0 - FFA7
8 bytes
Primary bus master IDE registers
FFA8 - FFAF
8 bytes
Secondary bus master IDE registers
Notes:
1.
Default, but can be changed to another address range
2.
Dword access only
3.
Byte access only
✏
NOTE
Some additional I/O addresses are not available due to ICH4 address aliassing.
The ICH4 data
sheet provides more information on address aliassing.
For information about
Refer to
Obtaining the ICH4 data sheet
Section 1.2 on page 12