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Block Diagram - lga775

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Intel Desktop Board D945GNT Technical Product Specification 1.1.4 Block Diagram Figure 2 is a block diagram of the major functional areas. PCI Express x1 Interface PCI Express x1 Slot 1 PCI Express x1 Slot 2 Parallel ATA IDE Connector Parallel ATA IDE Interface LGA775 Processor Socket System Bus (1066/800/533 MHz) PCI Express x16 Interface PCI Express x16 Connector Intel 945G Chipset Intel 82945G Graphics and Memory Controller Hub (GMCH) Gigabit Ethernet Controller (Optional) LAN Connector USB Back Panel/Front Panel USB Ports Legacy I/O Controller LPC Bus Serial Port Parallel Port PS/2 Mouse PS/2 Keyboard Diskette Drive Connector Intel 82801G I/O Controller Hub (ICH7) Serial Peripheral Interface (SPI) Flash Device DMI Interconnect High Definition Audio Link LAN Connect Interface VGA Port Channel A DIMMs (2) Display Interface Dual-Channel Memory Bus SMBus Channel B DIMMs (2) IEEE-1394a Connectors (optional) IEEE-1394a Controller (optional) PCI Bus LPC TPM Component Bus (Optional) 10/100 LAN PLC (Optional) LAN Connector Serial ATA IDE Interface Serial ATA IDE Connectors (4) PCI Slot 1 PCI Slot 2 PCI Slot 3 PCI Slot 4 PCI Bus SMBus Hardware Monitoring and Fan Control ASIC = connector or socket Audio Codec Line Out Mic In Line In/Retasking Jack Line Out/Retasking Jack Mic In/Retasking Jack Center and LFE/ Retasking Jack (optional) Surround L-R/ Retasking Jack (optional) S/PDIF (optional) Figure 2. Block Diagram OM17819 14

Section	Page
Intel® Desktop Board D945GNT Technical Product Specification	1
Revision History / Disclaimer	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Other Common Notation	4
Contents	5
1 Product Description	9
1.1 Overview	10
1.1.1 Feature Summary	10
1.1.2 Manufacturing Options	11
1.1.3 Board Layout	12
1.1.4 Block Diagram	14
1.2 Online Support	15
1.3 Processor	15
1.4 System Memory	16
1.4.1 Memory Configurations	17
1.5 Intel® 945G Chipset	21
1.5.1 Intel 945G Graphics Subsystem	21
1.5.2 USB	23
1.5.3 IDE Support	24
1.5.4 Real-Time Clock, CMOS SRAM, and Battery	26
1.6 PCI Express Connectors	26
1.7 IEEE-1394a Connectors (Optional)	26
1.8 Legacy I/O Controller	27
1.8.1 Serial Port	27
1.8.2 Parallel Port	27
1.8.3 Diskette Drive Controller	27
1.8.4 Keyboard and Mouse Interface	27
1.9 Audio Subsystem	28
1.9.1 Audio Subsystem Software	28
1.9.2 Audio Connectors	28
1.9.3 8-Channel (7.1) Audio Subsystem	29
1.9.4 6-Channel (5.1) Audio Subsystem	31
1.10 LAN Subsystem	32
1.10.1 LAN Subsystem Software	32
1.10.2 10/100 Mbits/sec LAN Subsystem	32
1.10.3 Gigabit LAN Subsystem	33
1.10.4 Intel Active Management Technology (Optional)	34
1.10.5 Alert Standard Format (ASF) Support (Optional)	36
1.11 Hardware Management Subsystem	36
1.11.1 Hardware Monitoring and Fan Control ASIC	37
1.11.2 Chassis Intrusion and Detection	37
1.11.3 Fan Monitoring	37
1.11.4 Thermal Monitoring	38
1.12 Power Management	39
1.12.1 ACPI	39
1.12.2 Hardware Support	41
1.13 Trusted Platform Module (Optional)	45
2 Technical Reference	47
2.1 Introduction	47
2.2 Memory Resources	47
2.2.1 Addressable Memory	47
2.2.2 Memory Map	49
2.3 DMA Channels	49
2.4 Fixed I/O Map	50
2.5 PCI Configuration Space Map	51
2.6 Interrupts	52
2.7 PCI Conventional Interrupt Routing Map	53
2.8 Connectors	55
2.8.1 Back Panel Connectors	55
2.8.2 Component-side Connectors	58
2.9 Jumper Block	67
2.10 Mechanical Considerations	68
2.10.1 Form Factor	68
2.10.2 I/O Shield	69
2.11 Electrical Considerations	71
2.11.1 DC Loading	71
2.11.2 Add-in Board Considerations	71
2.11.3 Fan Connector Current Capability	72
2.11.4 Power Supply Considerations	72
2.12 Thermal Considerations	73
2.13 Reliability	75
2.14 Environmental	76
2.15 Regulatory Compliance	77
2.15.1 Safety Regulations	77
2.15.2 EMC Regulations	77
2.15.3 European Union Declaration of Conformity Statement	78
2.15.4 Recycling Considerations	79
2.15.5 Product Certification Markings (Board Level)	80
3 Overview of BIOS Features	81
3.1 Introduction	81
3.2 BIOS Flash Memory Organization	82
3.3 Resource Configuration	82
3.3.1 PCI Autoconfiguration	82
3.3.2 PCI IDE Support	82
3.4 System Management BIOS (SMBIOS)	83
3.5 Legacy USB Support	83
3.6 BIOS Updates	84
3.6.1 Language Support	84
3.6.2 Custom Splash Screen	84
3.7 Boot Options	85
3.7.1 CD-ROM Boot	85
3.7.2 Network Boot	85
3.7.3 Booting Without Attached Devices	85
3.7.4 Changing the Default Boot Device During POST	85
3.8 Adjusting Boot Speed	86
3.8.1 Peripheral Selection and Configuration	86
3.8.2 BIOS Boot Optimizations	86
3.9 BIOS Security Features	87
4 Error Messages and Beep Codes	89
4.1 Speaker	89
4.2 BIOS Beep Codes	89
4.3 BIOS Error Messages	89

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Intel Desktop Board D945GNT Technical Product Specification

1.1.4

Block Diagram

Figure 2 is a block diagram of the major functional areas.

Intel 945G Chipset

Intel 82801G

I/O Controller Hub

(ICH7)

Intel 82945G

Graphics and

Memory Controller

Hub (GMCH)

Serial Peripheral

Interface (SPI)

Flash Device

System Bus

(1066/800/533 MHz)

LGA775

Processor Socket

Parallel ATA

IDE Connector

Diskette Drive

Connector

Legacy

I/O

Controller

PS/2 Keyboard

PS/2 Mouse

Parallel Port

Serial Port

Parallel ATA

IDE Interface

LPC

Bus

Hardware Monitoring

and Fan Control ASIC

OM17819

Audio

Codec

LAN

Connector

10/100

LAN PLC

(Optional)

PCI Express

x16 Interface

PCI Express

x16

Connector

= connector or socket

PCI Bus

SMBus

High Definition Audio Link

USB

Dual-Channel

Memory Bus

SMBus

PCI Slot 1

PCI Slot 2

PCI Slot 3

PCI Slot 4

Serial ATA IDE

Connectors (4)

Serial ATA

IDE Interface

VGA

Port

Display Interface

Channel A

DIMMs (2)

Channel B

DIMMs (2)

Back Panel/Front Panel

USB Ports

DMI Interconnect

TPM Component

(Optional)

LPC

Bus

LAN Connect

Interface

PCI Express x1 Slot 1

PCI Express x1 Slot 2

PCI Express x1 Interface

LAN

Connector

Gigabit Ethernet

Controller (Optional)

Line Out/Retasking Jack

Mic In

Line In/Retasking Jack

Mic In/Retasking Jack

S/PDIF (optional)

Surround L-R/

Retasking Jack (optional)

Center and LFE/

Retasking Jack (optional)

Line Out

PCI

Bus

IEEE-1394a Connectors

(optional)

IEEE-1394a

Controller

(optional)

Figure 2.

Block Diagram