Lenovo PC 300GL Technical Information Manual 6272, 6282 - Page 60

DMA I/O Address Map

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Appendix B. System Address Maps DMA I/O Address Map The following figure lists resource assignments for the DMA address map. Any addresses that are not shown are reserved. Figure 51 (Page 1 of 2). DMA I/O Addresses Address (Hex) Description 0000 Channel 0, Memory Address register 0001 Channel 0, Transfer Count register 0002 Channel 1, Memory Address register 0003 Channel 1, Transfer Count register 0004 Channel 2, Memory Address register 0005 Channel 2, Transfer Count register 0006 Channel 3, Memory Address register 0007 Channel 3, Transfer Count register 0008 Channels 0-3, Read Status/Write Command register 0009 Channels 0-3, Write Request register 000A Channels 0-3, Write Single Mask register bits 000B Channels 0-3, Mode register (write) 000C Channels 0-3, Clear byte pointer (write) 000D Channels 0-3, Master clear (write)/temp (read) 000E Channels 0-3, Clear Mask register (write) 000F Channels 0-3, Write All Mask register bits 0081 Channel 2, Page Table Address register 3 0082 Channel 3, Page Table Address register 3 0083 Channel 1, Page Table Address register 3 0087 Channel 0, Page Table Address register 3 0089 Channel 6, Page Table Address register 3 008A Channel 7, Page Table Address register 3 008B Channel 5, Page Table Address register 3 008F Channel 4, Page Table Address/Refresh register 00C0 Channel 4, Memory Address register 00C2 Channel 4, Transfer Count register 00C4 Channel 5, Memory Address register 00C6 Channel 5, Transfer Count register 00C8 Channel 6, Memory Address register 00CA Channel 6, Transfer Count register 00CC Channel 7, Memory Address register 00CE Channel 7, Transfer Count register 00D0 Channels 4-7, Read Status/Write Command register 00D2 Channels 4-7, Write Request register 00D4 Channels 4-7, Write Single Mask register bit 00D6 Channels 4-7, Mode register (write) 00D8 Channels 4-7, Clear byte pointer (write) 00DA Channels 4-7, Master clear (write)/temp (read) Bits 00-15 00-15 00-15 00-15 00-15 00-15 00-15 00-15 00-07 00-02 00-02 00-07 N/A 00-07 00-03 00-03 00-07 00-07 00-07 00-07 00-07 00-07 00-07 00-07 00-15 00-15 00-15 00-15 00-15 00-15 00-15 00-15 00-07 00-02 00-02 00-07 N/A 00-07 Byte Pointer Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 48 Technical Information Manual

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Appendix B.
System Address Maps
DMA I/O Address Map
The following figure lists resource assignments for the DMA address map.
Any addresses that are not
shown are reserved.
Figure 51 (Page 1 of 2). DMA I/O Addresses
Address (Hex)
Description
Bits
Byte Pointer
0000
Channel 0, Memory Address register
00–15
Yes
0001
Channel 0, Transfer Count register
00–15
Yes
0002
Channel 1, Memory Address register
00–15
Yes
0003
Channel 1, Transfer Count register
00–15
Yes
0004
Channel 2, Memory Address register
00–15
Yes
0005
Channel 2, Transfer Count register
00–15
Yes
0006
Channel 3, Memory Address register
00–15
Yes
0007
Channel 3, Transfer Count register
00–15
Yes
0008
Channels 0–3, Read Status/Write Command register
00–07
0009
Channels 0–3, Write Request register
00–02
000A
Channels 0–3, Write Single Mask register bits
00–02
000B
Channels 0–3, Mode register (write)
00–07
000C
Channels 0–3, Clear byte pointer (write)
N/A
000D
Channels 0–3, Master clear (write)/temp (read)
00–07
000E
Channels 0–3, Clear Mask register (write)
00–03
000F
Channels 0–3, Write All Mask register bits
00–03
0081
Channel 2, Page Table Address register
3
00–07
0082
Channel 3, Page Table Address register
3
00–07
0083
Channel 1, Page Table Address register
3
00–07
0087
Channel 0, Page Table Address register
3
00–07
0089
Channel 6, Page Table Address register
3
00–07
008A
Channel 7, Page Table Address register
3
00–07
008B
Channel 5, Page Table Address register
3
00–07
008F
Channel 4, Page Table Address/Refresh register
00–07
00C0
Channel 4, Memory Address register
00–15
Yes
00C2
Channel 4, Transfer Count register
00–15
Yes
00C4
Channel 5, Memory Address register
00–15
Yes
00C6
Channel 5, Transfer Count register
00–15
Yes
00C8
Channel 6, Memory Address register
00–15
Yes
00CA
Channel 6, Transfer Count register
00–15
Yes
00CC
Channel 7, Memory Address register
00–15
Yes
00CE
Channel 7, Transfer Count register
00–15
Yes
00D0
Channels 4–7, Read Status/Write Command register
00–07
00D2
Channels 4–7, Write Request register
00–02
00D4
Channels 4–7, Write Single Mask register bit
00–02
00D6
Channels 4–7, Mode register (write)
00–07
00D8
Channels 4–7, Clear byte pointer (write)
N/A
00DA
Channels 4–7, Master clear (write)/temp (read)
00–07
48
Technical Information Manual