MSI 790XT User Guide - Page 39

CAS Latency CL

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English ▶ DRAM Timing Mode This field has the capacity to automatically detect all of the DRAM timing. If you set this field to [DCT 0], [DCT 1] or [Both], some fields will appear and selectable. DCT 0 controls channel A and DCT1 controls channel B. ▶ CAS Latency (CL) When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjustable. This controls the CAS latency, which determines the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. ▶ tRCD When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjustable. When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. ▶ tRP When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjustable. This setting controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. ▶ tRAS When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjustable. This setting determines the time RAS takes to read from and write to a memory cell. ▶ tRTP When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjustable. This setting controls the time interval between a read and a precharge command. ▶ tRC When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjustable. The row cycle time determines the minimum number of clock cycles a memory row takes to complete a full cycle, from row activation up to the precharging of the active row. ▶ tWR When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjustable. It specifies the amount of delay (in clock cycles) that must elapse after the completion of a valid write operation, before an active bank can be precharged. This delay is required to guarantee that data in the write buffers can be written to the memory cells before precharge occurs. ▶ tRRD When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjustable. Specifies the active-to-active delay of different banks. En-29

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En-29
Engl±sh
DRAM T±m±ng Mode
Th±s field has the capac±ty to automat±cally detect all of the DRAM t±m±ng. If you set
th±s field to [DCT 0], [DCT 1] or [Both], some fields w±ll appear and selectable. DCT
0 controls channel A and DCT1 controls channel B.
CAS Latency (CL)
When the DRAM T±m±ng Mode sets to [DCT 0], [DCT1] or [Both], the field ±s
adjustable. Th±s controls the CAS latency, wh±ch determ±nes the t±m±ng delay (±n
clock cycles) before SDRAM starts a read command after rece±v±ng ±t.
tRCD
When the DRAM T±m±ng Mode sets to [DCT 0], [DCT1] or [Both], the field ±s adjustable.
When DRAM ±s refreshed, both rows and columns are addressed separately. Th±s
setup ±tem allows you to determ±ne the t±m±ng of the trans±t±on from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance.
tRP
When the DRAM T±m±ng Mode sets to [DCT 0], [DCT1] or [Both], the field ±s
adjustable. Th±s sett±ng controls the number of cycles for Row Address Strobe (RAS)
to be allowed to precharge. If ±nsuffic±ent t±me ±s allowed for the RAS to accumulate
±ts charge before DRAM refresh may be ±ncomplete and DRAM may fa±l to reta±n
data. Th±s ±tem appl±es only when synchronous DRAM ±s ±nstalled ±n the system.
tRAS
When the DRAM T±m±ng Mode sets to [DCT 0], [DCT1] or [Both], the field ±s
adjustable. Th±s sett±ng determ±nes the t±me RAS takes to read from and wr±te to a
memory cell.
tRTP
When the DRAM T±m±ng Mode sets to [DCT 0], [DCT1] or [Both], the field ±s
adjustable. Th±s sett±ng controls the t±me ±nterval between a read and a precharge
command.
tRC
When the DRAM T±m±ng Mode sets to [DCT 0], [DCT1] or [Both], the field ±s
adjustable. The row cycle t±me determ±nes the m±n±mum number of clock cycles a
memory row takes to complete a full cycle, from row act±vat±on up to the precharg±ng
of the act±ve row.
tWR
When the DRAM T±m±ng Mode sets to [DCT 0], [DCT1] or [Both], the field ±s
adjustable. It spec±fies the amount of delay (±n clock cycles) that must elapse after
the complet±on of a val±d wr±te operat±on, before an act±ve bank can be precharged.
Th±s delay ±s requ±red to guarantee that data ±n the wr±te buffers can be wr±tten to the
memory cells before precharge occurs.
tRRD
When the DRAM T±m±ng Mode sets to [DCT 0], [DCT1] or [Both], the field ±s
adjustable. Spec±fies the act±ve-to-act±ve delay of d±fferent banks.
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