MSI MS5169 User Guide - Page 40

USB Function, USB Keyboard Legacy Support, Ext. Tag SRAM Width, DRAM Timing, Pipe Function, Gated

Page 40 highlights

CHAPTER 3 AMI® BIOS USER’S GUIDE Description of the item on screen follows: USB Function Set this option to Enabled or Disabled the on-chip USB controller. The Optional and Fail-Safe default settings are Disabled. USB Keyboard Legacy Support Set this option to Enabled or Disabled USB keyboard/mouse. The Optional and Fail-Safe default settings are Disabled. Ext. Tag SRAM Width During 8 bits, the cacheable RAM is 64MB. During 10 bits, the cacheable RAM is 256MB. DRAM Timing Choose DRAM timing for customize setup. Pipe Function Set this option to Enabled the pipeline from the PCI bus to system memory. The settings are Enabled or Disabled. The Optimal and Fail-Safe Default settings are Enabled. Gated Clock Primary Frame Buffer The processor provides a write-combining with buffering strategy for write operation. This is useful for frame buffering. Writing to USWC memory can be buffered and combined in the processors write-combining buffer (WCB). The WCBs are viewed as a special purpose outgoing write buffers, rather than a cache. The WCBs are written into memory to allocate a different address, or after executing a serializing, locked, or I/O instructions. During Enabled, this will enable the processor memory location C000 and DFFF segment as USWC memory type. 3-10

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CHAPTER 3
AMI
®
BIOS USER±S GUIDE
3-10
Description of the item on screen follows:
USB Function
Set this option to Enabled or Disabled the on-chip USB controller.
The Optional and Fail-Safe default settings are Disabled.
USB Keyboard Legacy Support
Set this option to Enabled or Disabled USB keyboard/mouse.
The Optional and Fail-Safe default settings are Disabled.
Ext. Tag SRAM Width
During 8 bits, the cacheable RAM is 64MB.
During 10 bits, the
cacheable RAM is 256MB.
DRAM Timing
Choose DRAM timing for customize setup.
Pipe Function
Set this option to Enabled the pipeline from the PCI bus to system
memory.
The settings are Enabled or Disabled.
The Optimal and Fail-Safe
Default settings are Enabled.
Gated Clock
Primary Frame Buffer
The processor provides a write-combining with buffering strategy
for write operation.
This is useful for frame buffering.
Writing to USWC
memory can be buffered and combined in the processors write-combining
buffer (WCB).
The WCBs are viewed as a special purpose outgoing write
buffers, rather than a cache.
The WCBs are written into memory to allocate a
different address, or after executing a serializing, locked, or I/O instructions.
During Enabled, this will enable the processor memory location
C000 and DFFF segment as USWC memory type.