Panasonic BL-C111A Service Manual - Page 11

LAN Block, Camera Block - installation

Get Panasonic BL-C111A - Network Camera - Pan PDF manuals and user guides
UPC - 037988845149
View all Panasonic BL-C111A manuals
Add to My Manuals
Save this manual to your list of manuals

Page 11 highlights

BL-C111A/BL-C131A 4.1.2. LAN Block Consists of IC101 (CPU), IC105 (ETHER-PHY), T1 (Trans) and CN2 (RJ45). T1 (Trans) insulates sets and Ethernet. IC101 (CPU) and IC105 (ETHER-PHY) are connected by a signal called MIIBus which it makes it possible to transmit/receive Ethernet data. IC105 has Auto Negotiation Function which changes 100BASE-T or 10BASE-TX automatically. Transmitting Operation Electric signal from IC101 is changed to Ethernet data on IC105 and it is sent through T1 from CN2. Receiving Operation Ethernet data from CN2 is change to electrical signal on IC105 and it is received by IC101. 4.1.3. Camera Block This CMOS image sensor which consolidates sensor section and image process DSP consists of one chip. Each pixel which has a micro lens for increased sensibility. It changes optical energy to analogue voltage. After that, analogue pixel voltage is converted into digital using the 10 bit AD Converter (ADC). At that time, Correlated Double Sampling (CDS) dramatically decreases Formulaic Pattern Noise (FPN). Analogue pixel voltage data which is converted to digital is finished using Gammacorrection, Color Correction and Color Space Conversion. Those signals are sent out as digital format 8bit span Y/UV with PCLK, Hsync and Vsync signals as a timing interface. In addition, the Image Processing Function of AE (Auto Iris) and AWB (Auto White Balance) is installed and it is automatically operated following an algorithm in the chip. Exposure control (Auto Iris) is adjusted by shutter speed. Setting up of each chip register is set at I2C by CPU (IC101) on Main Board. CMOS color image sensor module (IC701) Operating Power Supply: +2.8V It is supplied by Main Board. (3 Terminal Regulator IC51) Package: 20pin module Image Sensor and its Process Circuit are installed. Available Number of Pixels: 640 x 480 pixels Image Area: 1/6 inch Optical Size Color Filter: RGB Beyer Alignment Input Clock: 27 MHz (It is supplied by IC101 of Main Board) 11

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
11
BL-C111A/BL-C131A
4.1.2.
LAN Block
Consists of IC101 (CPU), IC105 (ETHER-PHY), T1 (Trans) and CN2 (RJ45).
T1 (Trans) insulates sets and Ethernet.
IC101 (CPU) and IC105 (ETHER-PHY) are connected by a signal called MIIBus which it makes it possible to transmit/receive
Ethernet data.
IC105 has Auto Negotiation Function which changes 100BASE-T or 10BASE-TX automatically.
Transmitting Operation
Electric signal from IC101 is changed to Ethernet data on IC105 and it is sent through T1 from CN2.
Receiving Operation
Ethernet data from CN2 is change to electrical signal on IC105 and it is received by IC101.
4.1.3.
Camera Block
<Basic Circuit Operation>
This CMOS image sensor which consolidates sensor section and image process DSP consists of one chip. Each pixel which
has a micro lens for increased sensibility. It changes optical energy to analogue voltage. After that, analogue pixel voltage is
converted into digital using the 10 bit AD Converter (ADC). At that time, Correlated Double Sampling (CDS) dramatically
decreases Formulaic Pattern Noise (FPN).
Analogue pixel voltage data which is converted to digital is finished using Gammacorrection, Color Correction and Color Space
Conversion. Those signals are sent out as digital format 8bit span Y/UV with PCLK, Hsync and Vsync signals as a timing inter-
face. In addition, the Image Processing Function of AE (Auto Iris) and AWB (Auto White Balance) is installed and it is automati-
cally operated following an algorithm in the chip.
Exposure control (Auto Iris) is adjusted by shutter speed.
Setting up of each chip register is set at I2C
by CPU (IC101) on Main Board.
CMOS color image sensor module (IC701)
Operating Power Supply: +2.8V It is supplied by Main Board. (3 Terminal Regulator IC51)
Package: 20pin module
Image Sensor and its Process Circuit are installed.
Available Number of Pixels: 640 x 480 pixels
Image Area: 1/6 inch Optical Size
Color Filter: RGB Beyer Alignment
Input Clock: 27 MHz (It is supplied by IC101 of Main Board)