Sharp GX20 Service Manual - Page 141

IC106 LRS1B24: 4-LEVEL STACK MEMORY, Pin No., Terminal name, Input/Output, Description of terminal

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IC106 (LRS1B24): 4-LEVEL STACK MEMORY Pin No. 1 2 3 4 5 6 7 8 9 10* 11 12 13 14 15 16 17 18 19 20 21 22 Terminal name NC NC A20 A11 A15 A14 A13 A12 GND NC NC NC A16 A8 A10 A9 DQ15 S-/WE DQ14 DQ7 F-/WE RY/-BY Input/Output - - Input Input Input Input Input Input - - - - Input Input Input Input Input/Output Input Input/Output Input/Output Input Output 23 A21 24 S-A17 25 DQ13 26 DQ6 27 DQ4 28 DQ5 29 GND 30 /RST Input Input Input/Output Input/Output Input/Output Input/Output - Input 31 T1 - 32* T2 (NC) - 33 DQ12 Input/Output 34 CE2 Input 35 S-VCC - 36 F/SC-VCC - 37 /WP (F-/WP) Input 38 VPP (F-VPP) Input/- 39 A19 (F-A19) Input 40 DQ11 Input/Output 41 F/SC-VCC - 42 DQ10 Input/Output 43 DQ2 Input/Output 44 DQ3 Input/Output 45 /LB Input 46 /UB Input 47 S-/OE Input 48* T3(NC) - 49 DQ9 Input/Output 50 DQ8 Input/Output 51 DQ0 Input/Output 52 DQ1 Input/Output 53 A18 Input 54 F-A17 Input CONFIDENTIAL GX20 Description of terminal Not used Not used Address input (Flash, Smartcombo RAM) Address input (common) Address input (common) Address input (common) Address input (common) Address input (common) Ground Not used Not used Not used Address input (common) Address input (common) Address input (common) Address input (common) Data input/output (common) Write enable input (SRAM, Smartcombo RAM) Data input/output (common) Data input/output (common) Write enable input (Flash) Ready busy output (Flash) When deleting/writing: VOL When interrupting block delete/write: High-Z (High impedance) Address input (Flash, Smartcombo RAM) Address input (SRAM, Smartcombo RAM) Data input/output (common) Data input/output (common) Data input/output (common) Data input/output (common) Ground Reset power down input (Flash) When deleting/writing block: VIH When reading: VIH Reset power down: VIL Test pin (all open) Test pin (all open) Data input/output (common) Chip enable input (SRAM), sleep state input (Smartcombo RAM) Power (SRAM) Power (Flash, Smartcombo RAM) Write protect input (Flash) When WP is set to VIL, it is prohibited to cancel lock bit of the block that has lock bit down set. Deletion and program operation are executable for the block that has neither lock bit nor lock down bit set. Disable lock down bit by setting WP to VIH. Power voltage detect terminal (Flash) When deleting/writing: VPP = VPPH When deleting/writing is prohibited: VPP < VPPLK Address input (Flash, Smartcombo RAM) Data input/output (common) Power (Flash, Smartcombo RAM) Data input/output (common) Data input/output (common) Data input/output (common) SRAM, Smartcombo RAM byte enable input (DQ0 - DQ7) SRAM, Smartcombo RAM byte enable input (DQ8 - DQ15) Output enable input (SRAM, Smartcombo RAM) Test pin (all open) Data input/output (common) Data input/output (common) Data input/output (common) Data input/output (common) Address input (Flash, Smartcombo RAM) Address input (Flash) 6 - 9

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GX20
6 – 9
CONFIDENTIAL
IC106 (LRS1B24): 4-LEVEL STACK MEMORY
Pin No.
Terminal name
Input/Output
Description of terminal
1
NC
–
Not used
2
NC
–
Not used
3
A20
Input
Address input (Flash, Smartcombo RAM)
4
A11
Input
Address input (common)
5
A15
Input
Address input (common)
6
A14
Input
Address input (common)
7
A13
Input
Address input (common)
8
A12
Input
Address input (common)
9
GND
–
Ground
10*
NC
–
Not used
11
NC
–
Not used
12
NC
–
Not used
13
A16
Input
Address input (common)
14
A8
Input
Address input (common)
15
A10
Input
Address input (common)
16
A9
Input
Address input (common)
17
DQ15
Input/Output
Data input/output (common)
18
S-/WE
Input
Write enable input (SRAM, Smartcombo RAM)
19
DQ14
Input/Output
Data input/output (common)
20
DQ7
Input/Output
Data input/output (common)
21
F-/WE
Input
Write enable input (Flash)
22
RY/-BY
Output
Ready busy output (Flash)
When deleting/writing: VOL
When interrupting block delete/write: High-Z (High impedance)
23
A21
Input
Address input (Flash, Smartcombo RAM)
24
S-A17
Input
Address input (SRAM, Smartcombo RAM)
25
DQ13
Input/Output
Data input/output (common)
26
DQ6
Input/Output
Data input/output (common)
27
DQ4
Input/Output
Data input/output (common)
28
DQ5
Input/Output
Data input/output (common)
29
GND
–
Ground
30
/RST
Input
Reset power down input (Flash)
When deleting/writing block: VIH
When reading: VIH
Reset power down: VIL
31
T1
–
Test pin (all open)
32*
T2 (NC)
–
Test pin (all open)
33
DQ12
Input/Output
Data input/output (common)
34
CE2
Input
Chip enable input (SRAM), sleep state input (Smartcombo RAM)
35
S-VCC
–
Power (SRAM)
36
F/SC-VCC
–
Power (Flash, Smartcombo RAM)
37
/WP (F-/WP)
Input
Write protect input (Flash)
When WP is set to VIL, it is prohibited to cancel lock bit of the block that has lock bit down set.
Deletion and program operation are executable for the block that has neither lock bit nor lock
down bit set. Disable lock down bit by setting WP to VIH.
38
VPP (F-VPP)
Input/–
Power voltage detect terminal (Flash)
When deleting/writing: VPP = VPPH
When deleting/writing is prohibited: VPP < VPPLK
39
A19 (F-A19)
Input
Address input (Flash, Smartcombo RAM)
40
DQ11
Input/Output
Data input/output (common)
41
F/SC-VCC
–
Power (Flash, Smartcombo RAM)
42
DQ10
Input/Output
Data input/output (common)
43
DQ2
Input/Output
Data input/output (common)
44
DQ3
Input/Output
Data input/output (common)
45
/LB
Input
SRAM, Smartcombo RAM byte enable input (DQ0 – DQ7)
46
/UB
Input
SRAM, Smartcombo RAM byte enable input (DQ8 – DQ15)
47
S-/OE
Input
Output enable input (SRAM, Smartcombo RAM)
48*
T3(NC)
–
Test pin (all open)
49
DQ9
Input/Output
Data input/output (common)
50
DQ8
Input/Output
Data input/output (common)
51
DQ0
Input/Output
Data input/output (common)
52
DQ1
Input/Output
Data input/output (common)
53
A18
Input
Address input (Flash, Smartcombo RAM)
54
F-A17
Input
Address input (Flash)