HP Visualize J5000 hp Visualize J5000, J7000 workstations service handbook (a4 - Page 82

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Troubleshooting Identifying LCD-Indicated Conditions Table 3-1. Chassis Codes for J5xxx and J7xxx Workstations Ostat FLT FLT FLT FLT FLT FLT WRN FLT FLT FLT FLT FLT INI INI Code FRU CBF0 SYS BD CBF1 SYS BD CBF2 SYS BD CBF3 SYS BD CBF4 SYS BD CBF5 SYS BD CBFA SYS BD CBFB SYS BD CBFC SYS BD CBFD SYS BD CBFE SYS BD CBFF SYS BD CC0n SYS BD CC1n SYS BD Message Description HPMC initiated A High-Priority Machine Check entered the firmware HPMC handler. no OS HPMC IVA There is no HPMC vector for the operating system. Firmware will halt the CPU, requiring a power cycle to recover. bad OS HPMC len The size of the operating system HPMC handler is invalid. Firmware will halt the CPU, requiring a power cycle to recover. bad OS HPMC addr The operating system HPMC handler vector is invalid. Firmware will halt the CPU, requiring a power cycle to recover. bad OS HPMC cksm The operating system HPMC handler failed the checksum test. Firmware will halt the CPU, requiring a power cycle to recover. OS HPMC vector 0 The size of the operating system HPMC handler is zero. Firmware will halt the CPU, requiring a power cycle to recover. prev HPMC logged Firmware detected unread PIM data from a previous HPMC and will overwrite it. brnch to OS HPMC Branching to the operating system HPMC handler. OS HPMC br err Branch to the operating system HPMC handler failed. Firmware will halt the CPU, requiring a power cycle to recover. unknown check The firmware trap handler didn't detect an HPMC, LPMC, or TOC. HPMC during TOC A High-Priority Machine Check occurred during Transfer of Control processing. multiple HPMCs A High-Priority Machine Check occurred while processing another HPMC. CPUn OS rendezvs Slave CPU n entering the final rendezvous, waiting for the operating system to awaken it. CPUn early rend Slave CPU n entering the early rendezvous, waiting for the monarch CPU to initialize scratch RAM and other system state. 76 Chapter 3

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76
Chapter 3
Troubleshooting
Identifying LCD-Indicated Conditions
FLT
CBF0
SYS BD
HPMC initiated
A High-Priority Machine Check entered
the firmware HPMC handler.
FLT
CBF1
SYS BD
no OS HPMC IVA
There is no HPMC vector for the
operating system. Firmware will halt the
CPU, requiring a power cycle to recover.
FLT
CBF2
SYS BD
bad OS HPMC len
The size of the operating system HPMC
handler is invalid. Firmware will halt the
CPU, requiring a power cycle to recover.
FLT
CBF3
SYS BD
bad OS HPMC addr
The operating system HPMC handler
vector is invalid. Firmware will halt the
CPU, requiring a power cycle to recover.
FLT
CBF4
SYS BD
bad OS HPMC cksm
The operating system HPMC handler
failed the checksum test. Firmware will
halt the CPU, requiring a power cycle to
recover.
FLT
CBF5
SYS BD
OS HPMC vector 0
The size of the operating system HPMC
handler is zero. Firmware will halt the
CPU, requiring a power cycle to recover.
WRN
CBFA
SYS BD
prev HPMC logged
Firmware detected unread PIM data from
a previous HPMC and will overwrite it.
FLT
CBFB
SYS BD
brnch to OS HPMC
Branching to the operating system HPMC
handler.
FLT
CBFC
SYS BD
OS HPMC br err
Branch to the operating system HPMC
handler failed. Firmware will halt the
CPU, requiring a power cycle to recover.
FLT
CBFD
SYS BD
unknown check
The firmware trap handler didn’t detect
an HPMC, LPMC, or TOC.
FLT
CBFE
SYS BD
HPMC during TOC
A High-Priority Machine Check occurred
during Transfer of Control processing.
FLT
CBFF
SYS BD
multiple HPMCs
A High-Priority Machine Check occurred
while processing another HPMC.
INI
CC0
n
SYS BD
CPU
n
OS rendezvs
Slave CPU
n
entering the final
rendezvous, waiting for the operating
system to awaken it.
INI
CC1
n
SYS BD
CPU
n
early rend
Slave CPU
n
entering the early
rendezvous, waiting for the monarch CPU
to initialize scratch RAM and other
system state.
Table 3-1. Chassis Codes for J5xxx and J7xxx Workstations
Ostat
Code
FRU
Message
Description