IBM DBCA-204860 Hard Drive Specifications - Page 44

00h. Device 0 may be unable to accept commands until it has finished its reset procedure and is ready ( D R D Y = 1 ) . CSEL (Cable Select) This signal is monitored to determine the drive address, 0 or 1, when the jumper on the interface connector is at Position-3. (See Figure 36 on page 50.) When CSEL is ground or a low level, the drive works as address 0. When CSEL is open or a high level, the drive works as address 1. The signal level of CSEL to one drive should be different from the signal level to another drive on the same AT interface cable to avoid drive address 0-0 or 1-1 configuration. KEY Pin position 20 has no connection pin. It is recommended to close the respective position of the cable connector in order to avoid incorrect insertion by mistake. IORDY Indication to host that the drive is ready to complete current I/O cycle. This line is driven low at the falling edge of -DIOR or -DIOW, when H D D needs some additional WAIT cycle(s) to extend PIO cycle. This line can be connected to host IORDY signal in order to insert WAIT state(s) in the host PIO cycle. This is an Open-Drain output with 24 mA sink capability. 5V Power There are two input pins for + 5 V power supply, " + 5 V Logic" and " + 5 V Motor". " + 5 V Logic" is connected to the internal logic circuits and " + 5 V Motor" is connected to the spindle motor and motor driver. It is possible to turn on and off " + 5 V Logic " by an external switch circuit to reduce power consumption to the least possible. In this mode, a voltage drop out due to the motor spin up current can be reduced by connecting " + 5 V Motor" line into the system power source directly. If the host system while the H D D is disconnected from power line shall be isolated by Three-State line drivers. Internal leakage through ESD protection circuit may pull down LPUL (Least Positive Up Level) of logic signal below the spec. Use both lines in parallel, for regular H D D application. 5 volts. -DMACK This signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted, or that data is available. This signal is internally pulled-up to 5Volt through 15 K ohm resistor and the tolerance of the resistor value is -50% to + 1 0 0 % . DMARQ This signal, used for DMA data transfers between host and drive, shall be asserted by the drive when it is ready to transfer data to or from the host. The direction of data transfer is controlled by -HIOR and -HIOW. This signal is used on a handshake manner with -DMACK. This signal is a 3-state line with 24mA sink capability and internally pulled-down to G N D through 10 kΩ resistor. -HDMARDY (Ultra DMA) This signal is used only for Ultra D M A data transfers between host and drive. -HDMARDY is a flow control signal for Ultra D M A data in bursts. This signal is held asserted by the host to indicate to the device that the host is ready to receive Ultra D M A data in transfers. The host may negate -HDMARDY to pause an Ultra DMA data in transfer. HSTROBE (Ultra DMA) This signal is used only for Ultra D M A data transfers between host and drive. HSTROBE is the data out strobe signal from the host for an Ultra D M A data out transfer. Both the rising and falling edge of HSTROBE latch the data from DD(15:0) into the device. The host may stop toggling HSTROBE to pause an Ultra DMA data out transfer. 36 OEM Specifications of DBCA-2xxxxx 2.5 inch H D D