IBM DBCA-204860 Hard Drive Specifications - Page 47

PIO Timings

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6.5 PIO Timings The PIO cycle timings meet Mode 4 of the ATA-3 description. CS0, CS1 +DA0 2 DIOR, DIOW < T1 > < < < T9 > T0 > T2 > < T2I > Write data +DD00 15 < T3 > < T4 > Read data +DD00 15 IOCS16 +IORDY > T7 < < T5 > T6Z < T6 > T8 < < TA > > TRD < < TB > PARAMETER DESCRIPTION MIN MAX Note (nsec) (nsec) T0 Cycle time T1 CS0 1, +DA00 02 valid to DIOR, DIOW active T2 DIOR, DIOW pulse width T2I DIOR, DIOW recovery T3 +DD00 15 setup to DIOW high T4 DIOW high to +DD00 15 hold T5 +DD00 15 setup to DIOR high T6 DIOR high to +DD00 15 hold T6Z DIOR high to +DDOO 15 tristate T7 CS0 1, +DA00 02 valid to IOCS16 assertion T8 CS0 1, +DA00 02 invalid to IOCS16 negation T9 DIOR, DIOW high to CS0 1, +DA00 02 hold TRD Read data valid to +IORDY active TA DIOR, DIOW low to +IORDY low TB +IORDY pulse width 120 25 70 25 20 10 20 *1 5 30 30 30 10 0 35 1250 Note *1 : This value is applied only when +IORDY is not negated. When +IORDY is negated, TRD is applied. Figure 25. PIO cycle timings Electrical Interface Specifications 39

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6.5
PIO Timings
The PIO cycle timings meet Mode 4 of the ATA-3 description.
CS0, CS1
+DA0 2
<
T9
>
<
T1 > <
T0
>
DIOR, DIOW
<
T2
><
T2I
>
Write data
+DD00 15
<
T3
> < T4 >
Read data
+DD00 15
<
T5
> T6Z <
>
T7
<
T6
> T8 <
IOCS16
< TA
>
> TRD <
+IORDY
<
TB
>
MIN
MAX
Note
PARAMETER DESCRIPTION
(nsec) (nsec)
T0
Cycle time
120
T1
CS0 1, +DA00 02 valid to
DIOR, DIOW active
25
T2
DIOR, DIOW pulse width
70
T2I
DIOR, DIOW recovery
25
T3
+DD00 15 setup to
DIOW high
20
T4
DIOW high to +DD00 15 hold
10
T5
+DD00 15 setup to
DIOR high
20
*1
T6
DIOR high to +DD00 15 hold
5
T6Z
DIOR high to +DDOO 15 tristate
30
T7
CS0 1, +DA00 02 valid to
IOCS16 assertion
30
T8
CS0 1, +DA00 02 invalid to
IOCS16 negation
30
T9
DIOR, DIOW high to
CS0 1, +DA00 02 hold
10
TRD
Read data valid to +IORDY active
0
TA
DIOR, DIOW low to +IORDY low
35
TB
+IORDY pulse width
1250
Note *1 : This value is applied only when +IORDY is not negated. When +IORDY
is negated, TRD is applied.
Figure 25. PIO cycle timings
Electrical Interface Specifications
39