Intel VC820 Design Guide

Intel VC820 - Desktop Board Motherboard Manual

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  • Intel VC820 | Design Guide - Page 1
    Intel® 820 Chipset Design Guide July 2000 Order Number: 290631-004
  • Intel VC820 | Design Guide - Page 2
    Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications IBM/Intel Advanced Intel literature may be obtained by: calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel
  • Intel VC820 | Design Guide - Page 3
    ...1-1 1.1 About This Design Guide 1-1 1.2 References...1-2 1.3 System 2-1 2.2 Component Quadrant Layout 2-1 2.3 Intel® 820 Chipset Component Placement 2-3 2.4 Core 2-41 2.7.10 AGP Pull-ups 2-41 2.7.11 Motherboard / Add-in Card Interoperability 2-42 2.8 Hub Interface 2-43 2.8.1 Data
  • Intel VC820 | Design Guide - Page 4
    14.1 AC'97 Signal Quality Requirements 2-63 2.14.2 AC'97 Motherboard Implementation 2-63 2.15 USB ...2-65 2.16 ISA (82380AB 2-66 2.16.1 ICH GPIO connected -Layout Simulation 3-8 3.2.4 Place and Route Board 3-10 3.2.5 Post-Layout Simulation 3-13 Routing 3-23 iv Intel® 820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 5
    Specification ...........4-12 4.8.2 DRCG+ Frequency Selection Schematic 4-13 5 System Manufacturing 5-1 5.1 In Circuit LPC Flash BIOS Programming 5-1 5.2 LPC Flash BIOS Terminology and Definitions 6-1 6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery ......6-2 6.1.3 64/72Mbit
  • Intel VC820 | Design Guide - Page 6
    Hub Interface Reference Dividers 2-45 Intel® Pentium® III Processor Dual Processor Configuration 2-46 Intel® Pentium® III Processor Uni-Processor Configuration 2-46 Ground Plane Reference (Four Layer Motherboard 2-47 Hole Locations and Keepout Zones For Support Components 2-48 Grounding Pad
  • Intel VC820 | Design Guide - Page 7
    Topology AC'97 Trace Length Requirements 2-62 USB Data Signals 2-65 PCI Bus Layout Example Measurement 3-25 Intel® 820 Chipset Platform Clock Distribution 4-2 Intel® 820 Chipset 7 mil Stackup (Not Routable 5-5 4.5 mil Stackup 5-5 Intel® 820 Chipset Power Delivery Example 6-2 1.8V and 2.5V
  • Intel VC820 | Design Guide - Page 8
    for Motherboard Routing Lengths 4-8 External DRCG Component Values 4-10 Unused Output Termination 4-12 DRCG Ratio 4-12 28Ω Stackup Examples 5-3 3D Field Solver vs ZCALC 5-4 Intel® 820 Chipset Component Thermal Design Power 6-7 Glue Chip 3 Vendors 6-8 viii Intel® 820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 9
    have been updated (Appendix A). See the schematic revision history page at the end of Appendix A for details. - The following update is not uF to 0.047 uF. • Updated the text descriptions in the two paragraphs in Section 4.2.3, "MCH to DRCG". • Updated the first paragraph in Section 2.6.2.5,
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    This page is intentionally left blank. x Intel® 820 Chipset Design Guide
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    1 Introduction
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    This page is intentionally left blank.
  • Intel VC820 | Design Guide - Page 13
    for designing an Intel® 820 chipset based platform. The motherboard functional units are covered (e.g., chipset component placement, system bus routing, system memory layout, display cache interface, hub interface, IDE, AC'97, USB, interrupts, SMBUS, PCD, LPC/FWH Flash BIOS, and RTC). • Chapter
  • Intel VC820 | Design Guide - Page 14
    the third generation desktop chipset designed for Intel's SC242 architecture and the first chipset to support the 4X capability of the AGP 2.0 Interface Specification and 400 MHz Direct RDRAM. The 400 MHz, 16 bit, double clocked Direct RDRAM interface provides 1.6 GB/s access to main memory. A new
  • Intel VC820 | Design Guide - Page 15
    audio and modem coder/decoders (codecs) instead of the traditional ISA devices. The ISA bus can be implemented through the use of the optional 82380AB PCI-ISA bridge. The Intel® 820 chipset contains two core components: the Memory USB host controller, LPC interface controller, FWH Flash BIOS
  • Intel VC820 | Design Guide - Page 16
    Bus Master IDE controller • USB controller • I/O APIC • SMBus controller • FWH interface (FWH Flash BIOS) • LPC interface • and cost of the ISA subsystem. The Intel® 820 chipset platform with optional ISA support takes advantage of the 82380AB ISA bridge. 4 133 1-4 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 17
    AGP 2.0 82820 Memory Controller Hub (MCH) Main Memory 4 IDE Drives 2 USB Ports Hub Interface PCI Bus PCI Slots AC'97 Codec(s) (optional) AC'97 2.1 82801AA I/O Controller Hub (ICH) Keyboard, Mouse, FD, PP, SP, IR LPC I/F Super I/O FWH Flash BIOS GPIO Intel®820 Chipset Design Guide 1-5
  • Intel VC820 | Design Guide - Page 18
    Hub (MCH) Main Memory 4 IDE Drives 2 USB Ports AC'97 Codec(s) (optional) AC'97 2.1 Hub Interface PCI Bus PCI Slots 82801AA I/O Controller Hub (ICH) ISA Bridge (optional) ISA Slots Keyboard, Mouse, FD, PP, SP, IR Super I/O LPC I/F FWH Flash BIOS GPIO 1-6 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 19
    MCH) Main Memory 4 IDE Drives 2 USB Ports AC'97 Codec(s) (optional) AC'97 2.1 Hub Interface PCI Bus PCI Slots 82801AA I/O Controller Hub (ICH) ISA Bridge (optional) ISA Slots Keyboard, Mouse, FD, PP, SP, IR Super I/O LPC I/F GPIO FWH Flash BIOS blk3 Intel®820 Chipset Design Guide 1-7
  • Intel VC820 | Design Guide - Page 20
    memory architecture provides enhanced power management capabilities. The powerdown mode of operation enables Intel® 820 chipset based systems to cost-effectively support suspend-to-RAM. Streaming SIMD Extensions The Pentium III processor provides 70 new Streaming SIMD (single instruction, multiple
  • Intel VC820 | Design Guide - Page 21
    instruct the ICH to generate either an SMI#, NMI#, SERR#, or TCO interrupt. Function Disable The ICH provides the ability to disable the following functions: AC'97 Modem, AC'97 Audio, IDE, USB or SMBus. Once disabled, these functions no longer decode I/O, memory . Intel®820 Chipset Design Guide 1-9
  • Intel VC820 | Design Guide - Page 22
    supporting two codecs with independent PCI functions for audio and modem. Microphone input and left and right audio channels are supported for a high quality two-speaker audio solution. Wake on ring from suspend is also supported with an appropriate modem codec. 1-10 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 23
    system requirements, a device bay controller and USB hub could be integrated into the LPC super I/O component. For systems requiring ISA support, an ISA-IRQ to serial-IRQ converter is required. Potentially, this converter could be integrated into the super I/O. Intel®820 Chipset Design Guide 1-11
  • Intel VC820 | Design Guide - Page 24
    Introduction This page is intentionally left blank 1-12 Intel®820 Chipset Design Guide
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    2 Layout and Routing Guidelines
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    This page is intentionally left blank.
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    Layout/Routing Guidelines Layout/Routing Guidelines 2 This chapter documents motherboard layout and routing guidelines for Intel® 820 chipset based systems. This section does not discuss the quadrant layouts are designed for use during component placement. Intel®820 Chipset Design Guide 2-1
  • Intel VC820 | Design Guide - Page 28
    Interface Direct RDRAM Figure 2-2. ICH 241-uBGA Quadrant Layout (Top View) Pin #1 Corner PCI AC'97, SMBus ICH 241 uBGA Processor Hub Interface LPC IDE 2-2 Intel®820 Chipset Design Guide
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    1. The ATX placements and layouts shown in Figure 2-3 is recommended for single (UP) Intel® 820 chipset based system design. 2. The trace length limitation between critical connections will be Bus AGP MCH 2.0 Hub Interface Direct RDRAM RDRAM Termination ICH Intel®820 Chipset Design Guide 2-3
  • Intel VC820 | Design Guide - Page 30
    Layout/Routing Guidelines 2.4 Core Chipset Routing Recommendations Figure 2-4 and Figure 2-5 show MCH core routing examples. Figure 2-4. Primary Side MCH Core Routing Example (ATX) 2-4 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 31
    bus frequency. A source synchronous strobed interface uses strobe signals (instead of the clock) to indicate that data is valid. Refer to Figure 2-6 for an example. Intel®820 Chipset Design Guide 2-5
  • Intel VC820 | Design Guide - Page 32
    ) Threshold Threshold Strobe Strobe Some buses have more than one strobe (i.e., AGP). The AGP 1.0 specification (1X and 2X mode) employs 3 strobe signals. These three strobe signals are each used to 16]) are sampled on the rising and falling edges of AD_STB1. 2-6 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 33
    is designed to operate as a transmission line; all components, including the individual RDRAMs, are incorporated into the design to create a uniform bus structure that can support up to 33 devices (including the MCH) running at 800 MegaTransfers/second (MT/s). Intel®820 Chipset Design Guide 2-7
  • Intel VC820 | Design Guide - Page 34
    ) signal has changed the requirements for trace width and prepreg thickness for the Intel® 820 chipset platform (refer to Section 5.3, "Stackup Requirement" on page 5-1). at Vterm. All unpopulated slots must have continuity modules in place to ensure that the signals propagate to the termination
  • Intel VC820 | Design Guide - Page 35
    to meet this via loading requirement (i.e., dummy vias). Table 2-2. Placement Guidelines for Motherboard Routing Lengths Reference Trace Description Maximum Trace Length (in.) A MCH to first Space Space Space RSL Signal Trace Ground RSL Signal Trace Ground Intel®820 Chipset Design Guide 2-9
  • Intel VC820 | Design Guide - Page 36
    Ground Flood (Shaded area) Neckdown for BJT BJT Neckdown to pass vias 18 mil clock traces when not 14:6 14 on 6 Differential clock pair 2-10 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 37
    is not required. The Vterm power island should be at LEAST 50 mils wide. This voltage does not need to be supplied during suspend-to-RAM. Figure 2-13. Direct RDRAM Termination Terminator R-packs RSL Signals Vterm Intel®820 Chipset Design Guide 2-11
  • Intel VC820 | Design Guide - Page 38
    via. Refer to Section 2.6.2.7, "VIA Compensation" on page 2-23 for more information on Via Compensation. Figure 2-14. Direct Rambus* Termination Example 2 GND VIAS / Capacitor 2-12 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 39
    RSL traces. Any split in the ground island will provide a sub-optimal return path. In a 4 layer board, this will require the Vterm island to be on an outer layer. The Vterm island should ALWAYS be placed connect the ground isolation on the 1st and 4th layers. Intel®820 Chipset Design Guide 2-13
  • Intel VC820 | Design Guide - Page 40
    # RCTM# LCFM# RCFM# RROW[2:0] RCOL[4:0] LDQA[8:0] LDQB[8:0] CMD This can be achieved on the motherboard by adding a copper tab to the specified RSL pins at each connector. The target value is approximately tab areas. Table 2-3 shows example copper tab areas. 2-14 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 41
    the RIMM pins must not be interrupted by the capacitor tabs, and they must be connected to avoid discontinuity in the ground plane as shown. Intel®820 Chipset Design Guide 2-15
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    Layout/Routing Guidelines Figure 2-17. Connector Compensation Example S E C T I O N A MCH 2-16 S E C T I O N B Intel®820 Chipset Design Guide
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    Figure 2-18. Section A1, Top Layer Outer C-tab Layout/Routing Guidelines Inner C-tab NOTES: 1. Refer to Figure 2-17. Ground flood removed from picture for clarity Intel®820 Chipset Design Guide 2-17
  • Intel VC820 | Design Guide - Page 44
    Layout/Routing Guidelines Figure 2-19. Section A1, Bottom Layer NOTES: 1. Refer to Figure 2-17. Ground flood removed from picture for clarity 2-18 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 45
    Figure 2-20. Section B1, Top Layer Layout/Routing Guidelines NOTES: 1. Refer to Figure 2-17. Ground flood removed from picture for clarity Intel®820 Chipset Design Guide 2-19
  • Intel VC820 | Design Guide - Page 46
    the second RIMM as shown in Figure 2-22 (signal A). Signals to the termination resistors can be routed on either layer from the last RIMM. 2-20 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 47
    the pad to the ball, the routing can compensate for this package mismatch. Therefore, the board length mismatch can be increased. The RSL channel requires matching trace lengths from pad-to-pin within 10 mils). ALL RSL signals must meet the following equation. Intel®820 Chipset Design Guide 2-21
  • Intel VC820 | Design Guide - Page 48
    L3, L4 -> Board Trace Length L1 MCH Package MCH Die Ball L3 L2 L4 L1 + L3 = Nominal RSL Length ±10 mils L2 + L4 = Nominal RSL Length ±10 mils R R I I M M M M C C o o n n n n e e c c t t o o V r r t e r m NOTE: Refer to the Intel® 820 Chipset: Intel® 82820 Memory
  • Intel VC820 | Design Guide - Page 49
    via (near the BGA pad) because some of the RSL signals must be routed on the bottom of the motherboard. Therefore, it is necessary to place a dummy via on all signals that are routed on the top layer. Note: 2000 mils was chosen as an EXAMPLE Nominal RSL Length. Intel®820 Chipset Design Guide 2-23
  • Intel VC820 | Design Guide - Page 50
    B max: Motherboard Trace = (Nominal RSL Length - Package Dimension) + 10 mil + 25 mil 9. Formula C: Motherboard Trace = (Nominal RSL Length - Package Dimension) * 1.021 10.Formula D: Motherboard Trace = (Nominal RSL Length - Package Dimension + 25 mil) * 1.021 2-24 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 51
    the MCH. • The resistors must be 91 Ω pullup and 39 Ω pulldown; they also must 2% or better for S3 mode reliability. The trace impedances remain 28 Ω. Intel®820 Chipset Design Guide 2-25
  • Intel VC820 | Design Guide - Page 52
    routed with a standard 5 mil wide 60 Ω trace. The motherboard routing lengths for the SIO signal are the same as RSL 10KΩ 0.4" - 0.45" Suspend-to-RAM Shunt Transistor When an Intel® 820 chipset system enters or exits Suspend-to-RAM, power will be ramping to the MCH Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 53
    MCH PWROK R I VCC5SBY 175 mils 175 mils M M S 2N3904 2N3904 SCK MCH 18 mils wide 5 mils wide 18 mils wide R I M M S 175 175 mils mils 2N3904 CMD Intel®820 Chipset Design Guide 2-27
  • Intel VC820 | Design Guide - Page 54
    " for Intel® 820 chipset platform Direct Rambus* clock routing guidelines. 2.6.6 Direct Rambus* Design Checklist Use the following checklist as a final check to ensure the motherboard incorporates solid capacitors must have AT LEAST 2 vias/cap to ground 2-28 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 55
    routed directly below the ground isolation split on the 3rd layer) - Uniform ground isolation flood is exactly 6 mils from the RSL signals at all times Intel®820 Chipset Design Guide 2-29
  • Intel VC820 | Design Guide - Page 56
    Nominal RSL Length (note: use the table in the Intel® 820 chipset: 82820 Memory Controller Hub (MCH) Datasheet to verify trace lengths). secondary side of the motherboard. "A" side RIMM connector signals are routed on the primary side of the motherboard. - Signals must " Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 57
    capability, are included in the AGP Interface Specification, Revision 2.0. The Intel® 820 chipset is the first Intel chipset that supports the enhanced features of AGP 2.0. The 4X 570 mv. Without proper isolation, crosstalk could create signal integrity issues. Intel®820 Chipset Design Guide 2-31
  • Intel VC820 | Design Guide - Page 58
    mode ONLY) Set #2 - AD[31:16] - C/BE[3:2]# - AD_STB1 - AD_STB1# (used in 4X mode ONLY) Set #3 - SBA[7:0] - SB_STB - SB_STB# (used in 4X mode ONLY) • Miscellaneous, Async - USB+ - USB- OVRCNT# - PME# - TYPDET# - PERR# - SERR# - INTA# - INTB# Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 59
    line length and length mismatch requirements are dependent on the routing rules used on the motherboard. These routing rules were created to give design freedom by making tradeoffs between signal those strobe signals (e.g., SBA[7:0]), can be 3.7" to 4.7" long. Intel®820 Chipset Design Guide 2-33
  • Intel VC820 | Design Guide - Page 60
    to each other). The two strobes in a strobe pair should be routed on 5 mil traces with at least 20 mils of space (1:4) between them. 2-34 Intel®820 Chipset Design Guide
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    , SB_STB# must be the same length NOTES: 1. Each strobe pair must be separated from other signals by at least 20 mils 2. These guidelines apply to board stackups with 10% impedance tolerance Intel®820 Chipset Design Guide 2-35
  • Intel VC820 | Design Guide - Page 62
    originates on the motherboard, add-in card, and clock synthesizer motherboard is allotted 0.9 ns of clock skew (the motherboard designer shall determine how the 0.9 ns is allocated between the board and the synthesizer). For Intel described in the AGP Design Guide, Revision 1.0 (Section 1.5.3.3).
  • Intel VC820 | Design Guide - Page 63
    (or to an AGP video controller if implemented as a board layout. An ideal design would have the complete AGP interface signal field referenced to ground. The recommendations above are not specific to any particular PCB stackup, but are applied to all Intel motherboard, there is no distinction between VCC
  • Intel VC820 | Design Guide - Page 64
    for low-voltage (1.5V) operation. The AGP 2.0 Specification implements a TYPEDET# (type detect) signal on the AGP connector that determines the operating voltage of the AGP 2.0 interface (VDDQ). The motherboard must provide either 1.5V or 3.3V to the add-in card depending on the state of the TYPEDET
  • Intel VC820 | Design Guide - Page 65
    must be matched in length to the strobe lines within 0.5 inches on the motherboard and within 0.25 inches on the add-in card. The voltage divider networks consists of AC and DC elements as shown in of 25 mils to reduce cross-talk and maintain signal integrity. Intel®820 Chipset Design Guide 2-39
  • Intel VC820 | Design Guide - Page 66
    Figure 2-32. AGP 2.0 VREF Generation & Distribution 1.5V AGP Card +12V O R7 1K Note: R7 is the same resistor R2 R4 1K 82 500pF C9 3.3V AGP Card VrefCG The resistor dividers should be placed near the for 3.3V add-in cards) and the source generated VREF (for 1.5V add-in cards). Usage of the
  • Intel VC820 | Design Guide - Page 67
    supports resistive buffer compensation (RCOMP). Tie the GRCOMP pin to a 40 Ω 2% (or 39 Ω 1%) pull-down resistor (to ground) via a 10 mil wide, very short (
  • Intel VC820 | Design Guide - Page 68
    specification): • USB+ • USB• OVRCNT# The following signal is a special AGP signal. It is either Grounded or No Connected on an AGP card. • TYPEDET# Note: All other signals on the AGP interface are in the VDDQ group. They are not 3.3V tolerant during 1.5V AGP operation. 2.7.11 Motherboard / Add-in
  • Intel VC820 | Design Guide - Page 69
    signal group to which it belongs. Figure 2-33. Hub Interface Signal Routing Example 1.8V O 10 KΩ HL11 ICH HL_STB HL_STB# HL[10:0] CLK66 GCLK MCH Clocks Intel®820 Chipset Design Guide 2-43
  • Intel VC820 | Design Guide - Page 70
    be chosen to ensure that the reference voltage tolerance is maintained over the entire input leakage specification. The recommended range for the resistor value is from minimum 100 ohm to maximum 1K ohm HUBREF MCH 0.01uF 300Ω HubRef1.vsd 0.01uF HUBREF ICH 0.1uF Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 71
    interface compensation (HLCOMP). HLCOMP is used by the ICH to adjust buffer characteristics to specific board characteristics. Refer to the ICH Datasheet for details on compensation. It can be used either the RCOMP method or ZCOMP method described for the ICH. Intel®820 Chipset Design Guide 2-45
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    base board. An Intel® Intel® 820 chipset designs, a termination card must be placed in the unused slot when only one processor is populated. This is necessary to ensure signal integrity requirements are met. Figure 2-36. Intel Figure 2-37. Intel® Pentium® III
  • Intel VC820 | Design Guide - Page 73
    return path. In a 4 layer board, this will require the VCCID island to be on an outer signal layer. Figure 2-38 shows a four layer motherboard power plane with ground reference for 159" mounting holes is for the supported plastic fastener attachment mechanism. Intel®820 Chipset Design Guide 2-47
  • Intel VC820 | Design Guide - Page 74
    to the motherboard will be touching the solder mask on the top layer of the board, and possibly short out traces immediately beneath the solder mask, resulting in board failure. The required thickness of the pad is less than 0.001" (using 1/2 oz. copper). 2-48 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 75
    resistor to ITP Connect to 2nd processor RP# RS[2:0]# 1 Leave as N/C (not supported by chipset). Connect to MCH Leave as N/C Connect to 2nd processor RSP# TRDY# 1 Leave as N/C (not supported by chipset). Connect to MCH Leave as N/C Connect to 2nd processor Intel®820 Chipset Design Guide 2-49
  • Intel VC820 | Design Guide - Page 76
    Connect to 2nd processor Connect to 2nd processor 150 Ω pull up to Vcc2.5, connect to ICH and FWH Flash BIOS 150 Ω pull up to Vcc2.5, connect to ICH 150 Ω pull up to Vcc2.5, connect to ICH Connect optional for signal integrity. See Connect to 2nd processor 2-50 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 77
    driver characteristics). To reduce pin-to-pin skew, tie host clock outputs together at the clock driver driver MHz support: 220 . Connect to on-board VR or VRM. supports Intel® Pentium® II processors at all current speeds, Intel® Pentium® III processors to a FMB guideline of 19.3A, and future Intel
  • Intel VC820 | Design Guide - Page 78
    buffer 100 nH SC242 Connector A motherboard trace 56 pF SC242 Connector B motherboard trace 56 pF itp vsd Table 2-14. Bus Request Connection Scheme for DP Intel® 820 Chipset Designs Bus Signal BREQ Strapping Requirements CPU #1 BREQ0# BREQ1# No Connect 2-52 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 79
    an example of the BREQ connections in a DP system. It is a requirement that the on-board logic tri-state BREQ0# after the arbitration ID strapping is complete. Additionally, BREQ0# and BREQ1# datasheets for complete description on the timing requirement. Intel®820 Chipset Design Guide 2-53
  • Intel VC820 | Design Guide - Page 80
    the overall system performance will be degraded. Also, Intel does not guarantee the above layout recommendation will are met. It is recommended that prototype boards implement the ITP connector. Logic Analyzer preclude use of the Intel Pentium III processor LAI. The Intel Pentium III processor LAI
  • Intel VC820 | Design Guide - Page 81
    as 5V PCI. • Select a board stack-up that minimizes the coupling between and decoupling are contained in "Slot 1 Processor Power Distribution Guidelines decoupling are contained in "Slot 1 Processor Power Distribution Guidelines may violate the ringback specifications. This "wired-OR" situation should be
  • Intel VC820 | Design Guide - Page 82
    chassis path between the motherboard ground and hard disk • PC99 requirement: Support Cable Select for master Specification SFF-8049. This specification can be obtained from the Small Form Factor Committee. To determine if ATA/66 mode can be enabled, the Intel® 820 chipset requires the system BIOS
  • Intel VC820 | Design Guide - Page 83
    Intel® 820 chipset can use two methods to detect the cable type. Each mode requires a different motherboard layout. Host-Side Detection (BIOS so that 5 volts will not be driven to the ICH or FWH Flash BIOS pins. The proper value of the series resistor is 15 KΩ (as Intel®820 Chipset Design Guide 2-57
  • Intel VC820 | Design Guide - Page 84
    (BIOS Queries IDE Drive for Cable Type) Device side detection requires only a 0.047 uF capacitor on the motherboard as type to the BIOS when it sends the IDENTIFY_DEVICE packet during system boot as described in the ATA/66 specification. Figure 2-47. uF capacitor 2-58 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 85
    Layout/Routing Guidelines Figure 2-48. Layout for Host- or Drive-Side IDE Cable Detection ICH Figure 2-49. Ultra ATA/66 Cable R1 R2 C1 id 1 d IDE Connector Black wires are ground Grey wires are signals Intel®820 Chipset Design Guide 2-59
  • Intel VC820 | Design Guide - Page 86
    on RESET#. The correct value should be determined for each unique motherboard design, based on signal quality. • An 8.2 KΩ to 10 the ATA-4 specification). • A 5.6 KΩ pull-down resistor is required on PDDREQ# and SDDREQ# (as required by the ATA-4 specification). • A Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 87
    the link, it must be the only codec. If an AC is on the link, another AC cannot be present. Intel has developed a common connector specification known as the Audio/Modem Riser (AMR). This specification defines a mechanism for allowing OEM plug-in card options. Intel®820 Chipset Design Guide 2-61
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    AMR specification provides a mechanism for AC'97 codecs to be on a riser card. This is important for modem codecs as it helps ease international certification of the modem. For -Chain Topology AC'97 Trace Length Requirements A ICH 5" Max M R 3" Max Codec 2-62 Intel®820 Chipset Design Guide
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    used as the timebase for latching and driving data. On the Intel® 820 chipset platform, the ICH supports Wake on Ring from S1, S3, and S4 via the AC to meet the AC'97 2.1 specification with the specified load of 50pF. 2.14.2 AC'97 Motherboard Implementation The following design considerations are
  • Intel VC820 | Design Guide - Page 90
    . • AMR Slot Special Connections - AUDIO_MUTE#: No connect on the motherboard. - AUDIO_PWRDN: No connect on the motherboard. Codecs on the AMR card should implement a powerdown pin, per the AC'97 2.1 specification, to control the amplifier. - MONO_PHONE: Connect top onboard audio codec if supported
  • Intel VC820 | Design Guide - Page 91
    the recommended USB schematic. Figure 2-54. USB Data Signals Driver 15 ohm P+ < 1" Motherboard Trace 45 ohm 47 pf 15k Driver 15 ohm < 1" P- Motherboard Trace 45 ohm 47 pf 15k USB Connector 90 ohm ICH Transmission Line USB Twisted Pair Cable Intel®820 Chipset Design Guide 2-65
  • Intel VC820 | Design Guide - Page 92
    Layout/Routing Guidelines Recommended USB trace characteristics • Impedance 'Z0' = 45.4 Ω • Line Delay = 160.2 ps • the 82380AB from subtractively decoding cycles on the PCI bus. The BIOS must configure the 82380AB, program the ICH to positively decode LPC 2-66 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 93
    drives heartbeat messages until the BIOS programs these signals as GPIOs). with the PCI Local Bus Specification Revision 2.2. The implementation is Specification Revision 2.2. The ICH supports six PCI Bus masters ( the ICH supports two PC/PCI storing system data in its RAM when the system is powered
  • Intel VC820 | Design Guide - Page 94
    = (C2 * C3)/(C2+C3) + Cparasitic C3 can be chosen such that C3 > C2. Then C2 can be trimmed to obtain the 32.768 kHz. 2-68 Intel®820 Chipset Design Guide
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    the external components (unless on the other side of the board). • The oscillator VCC should be clean; use a battery connection to maintain its functionality and its RAM while the ICH is not powered by the standby power supply should be used in a desktop system to provide continuous power to the RTC
  • Intel VC820 | Design Guide - Page 96
    1, and remains set until software clears it. As a result of this, when the system boots, the BIOS knows that the RTC battery has been removed. Figure 2-58. RTCRST External Circuit for the ICH RTC VCC3_3SBY (unless on the other side of the ground plane) 2-70 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 97
    or even stop completely. • To minimize noise of VBIAS, it is necessary to implement the routing guidelines described above and the required external RTC circuitry. Intel®820 Chipset Design Guide 2-71
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    Layout/Routing Guidelines This page is intentionally left blank. 2-72 Intel®820 Chipset Design Guide
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    3 Advanced System Bus Design
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  • Intel VC820 | Design Guide - Page 101
    specific system guidelines. This is a step-by-step methodology that Intel has successfully used to design high performance desktop (but are not limited to): clock to output time, output driver edge rate, output drive current, and input drive current. Discussion Intel®820 Chipset Design Guide 3-1
  • Intel VC820 | Design Guide - Page 102
    specifications; i.e., ringback, etc.), and the output pin of the driving agent crossing VREF if the driver was driving the Test Load used to specify the driver causes include variation of the board dielectric constant, changes in Manual for more details of GTL+. 3-2 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 103
    Network The trace of a Printed Circuit Board (PCB) that completes an electrical connection be due to reflections, driver oscillations, etc. See the respective processor's datasheet for ringback specification. Settling Limit Defines the maximum , and VREF noise. Intel®820 Chipset Design Guide 3-3
  • Intel VC820 | Design Guide - Page 104
    - Estimate Component to Component Spacing for AGTL+ Signals - Layout and Route Board • Post-Layout Simulation - Interconnect Extraction - Inter-Symbol Interference (ISI), Cross-talk, and Monte Carlo Analysis • Validation - Measurements - Determining Flight Time 3-4 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 105
    and clock jitter are needed, along with the component specifications. These equations contain a multi-bit adjustment factor, datasheet and thePentium® III Processor Developer's Manual for more details. Solving these equations for THOLD + CLKSKEW - TCO_MIN + MADJ Intel®820 Chipset Design Guide 3-5
  • Intel VC820 | Design Guide - Page 106
    driver and receiver. Table 3-1. AGTL+ Parameters for Example Calculations1,2 IC Parameters Intel the Pentium® II Processor Developer's Manual with the additional requirements noted in the expected signal propagation rate of a board are included in Section 3.2, "AGTL+ Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 107
    driver specification is being used.) • CLKJITTER = 0.250 ns Some clock driver components may not support ganging the outputs together. Be sure to verify with your clock component vendor before ganging the outputs. See the appropriate Intel include: - The effective board propagation constant (SEFF),
  • Intel VC820 | Design Guide - Page 108
    Independent) Driver Processor2 specification the base board (see Intel. By basing board layout guidelines on the solution space, the iterations between layout and post-layout simulation can be reduced. Intel others such as driver strength, package signal quality specifications. To establish
  • Intel VC820 | Design Guide - Page 109
    results in more noise than positioning them towards the ends. However, Intel has shown that drivers located in all positions (given appropriate variations in the other network parameters the simulator's net description or topology file generally does this. Intel®820 Chipset Design Guide 3-9
  • Intel VC820 | Design Guide - Page 110
    interconnect distances, verify that the placement can support the system timing requirements. The required bus Intel strongly recommends running analog simulations to ensure that each design has adequate noise and timing margin. Layout and Route Board Route the board 10 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 111
    topology and component placement location; therefore, constraining the board routing. These issues are not directly addressed in this document. Section 1.2, "References" on page 1-2 contains a listing of several documents that address some of these issues. Intel®820 Chipset Design Guide 3-11
  • Intel VC820 | Design Guide - Page 112
    driver as possible. The value of the series resistor is dependent on the clock driver driver to the Intel driver to SC242 connector Clock driver to Intel 82820 MCH H H + (clock delay from the processor edge to core) + connector delay 3.2.4.4 APIC Data Bus Routing Intel 2.5V Intel® 820
  • Intel VC820 | Design Guide - Page 113
    board from the CAD layout tools. Run simulations to verify that the layout meets timing and noise requirements. A small amount of "tuning" may be required; experience at Intel the opposite case is also valid). When the driver drives high on the first cycle and low Intel®820 Chipset Design Guide 3-13
  • Intel VC820 | Design Guide - Page 114
    simulation assumptions. 3.2.6.1 Measurements Note that the AGTL+ specification for signal quality is at the pad of the at the input pin of the receiver, and the output pin of the driver crossing VREF were it driving a test load. The timings in the tables and 3-14 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 115
    numbers. These measurements include all of the effects pertaining to the driver-system interface and the same is true for the TCO. Therefore the ). • Edge rate specifications. • Ringback specifications. • Overshoot/Undershoot specifications. • Settling Limit. Intel®820 Chipset Design Guide 3-15
  • Intel VC820 | Design Guide - Page 116
    support: • The range of timings for each of the agents in the system. - Clock to output [TCO]. (Note that the system load is likely to be different from the "specification the specification.) - board [SEFF]. - The board AGTL+ bus, a driver on the aggressor network 3-4 shows a driver on the aggressor
  • Intel VC820 | Design Guide - Page 117
    up to a maximum that is dependent on the rise/fall time of the aggressor's signal. Backward cross-talk reaches a maximum (and remains constant) when the Intel®820 Chipset Design Guide 3-17
  • Intel VC820 | Design Guide - Page 118
    is 3 V/ns and board delay is 175 ps/inch -talk from segments on two sides of a driver. The pulses from the backward cross-talk travel cross-talk to double. Potential Termination Cross-Talk Problems The use of commonly used "pull-up" at each resistive load. Intel recommends using discrete resistors,
  • Intel VC820 | Design Guide - Page 119
    ZEFF = Z0 1+ CD C0 (Ω) Equation 3-11. Distributed Trace Capacitance C0 = S0 Z0 (pF/ft) Equation 3-12. Distributed Trace Inductance L0 = 12∗Z0∗ S0 (nH/ft) Intel®820 Chipset Design Guide 3-19
  • Intel VC820 | Design Guide - Page 120
    on an unloaded PCB in ns/ft. This is referred to as the board propagation constant. • S0 MICROSTRIP and S0 STRIPLINE refer to the speed of distribute the required voltages. Refer to the Flexible Motherboard Power Distribution Guidelines for more information on power Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 121
    A Ground Plane Signal Layer B l 1 fl d Figure 3-8. Layer Switch with Multiple Reference Planes (same type) Signal Layer A Ground Plane Layer Layer Ground Plane Signal Layer B l M lt f l d Intel®820 Chipset Design Guide 3-21
  • Intel VC820 | Design Guide - Page 122
    have close proximity decoupling between the three reference planes. • A signal that transitions from a stripline or microstrip through vias or pins to a component (Intel 82820 MCH, etc.) should have close proximity decoupling across all involved reference planes to ground for the device. 3-22
  • Intel VC820 | Design Guide - Page 123
    the clock signal quality requirements. To help meet these specifications, follow these general guidelines: • Tie clock driver outputs if clock buffer supports this mode of operation. • Match the electrical each trace is likely to be. Maintaining an equal length Intel®820 Chipset Design Guide 3-23
  • Intel VC820 | Design Guide - Page 124
    of the driver and noise sources: • Motherboard coupling • VTT noise Intel®Pentium® II Processor Developer's Manual states that extrapolations should be made from the last crossing of the overdrive region back to VREF. Simulations performed on this topology 3-24 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 125
    VREF. The minimum flight time for a rising edge is measured from the time the driver crosses VREF when terminated to a test load, to the time when the signal Figure 3-12. Rising Edge Flight Time Measurement Receiver Pin Driver Pin into Test Load VREF+ 200 mV VVRREEFF-+1100V0R0EmmF VV∆VREF ∆
  • Intel VC820 | Design Guide - Page 126
    ahead and leaving the necessary time available for correctly designing a board layout will provide the designer with the best chance of integrity. Intel recommends planning a layout schedule that allows time for each of the tasks outlined in this document. 3-26 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 127
    4 Clocking
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  • Intel VC820 | Design Guide - Page 129
    PCI, LPC, FWH Flash PCICLK[1-7,F] BIOS Bus Clock ICH PCICLK 33 MHz FWH Flash BIOS Interface Clock FWH Flash BIOS CLK 3.3V LPC slot N/A CLK66 CLK N/A 66 MHz 3.3V 2 REF[0-1] Internal ICH Logic ICH Internal Super I/O Logic Super I/O CLK14 Vendor Specific 14 MHz 3.3V 1 48 MHz USB
  • Intel VC820 | Design Guide - Page 130
    PHASEINFO G APICCLK ICH H PCICLK I CLK66 J CLK14 K CLK48 L CLK PCI SLOTS L CLK PCI SLOTS L CLK PCI SLOTS L CLK PCI SLOTS PHASEINFO Q REFCLK DRCG P CLK AGP CONNECTOR N CLK FWH Flash BIOS M CLK LPC * The free-running PCI clock should be connected to the ICH. 4-2 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 131
    Intel® 820 Chipset Platform Clock Skews Skew Clock Symbols See Figure 4-1 Relationship Pin-to-Pin (ps) Board +2000 5 +375 6 NOTES: 1. DP Only 2. UP: MCH and CPU clock drivers are tied together to eliminate pin-to-pin skew. -175 and +175 pin-to-pin skew only Intel®820 Chipset Design Guide 4-3
  • Intel VC820 | Design Guide - Page 132
    Clock for Z AGP Slot PCI Clock for Z PCI Slots 3V66 Clock for Z MCH and ICH Z PCI Clock for ICH 1.5" 4" 4" ±TBD3 ±0" ±0" PCI Clock for On-Board Z Devices (excluding Revision 2.2 Specification which allows for a maximum of ±2ns clock skew. 820 lk t d 4-4 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 133
    Table 4-3. Intel® 820 Chipset Platform System Clock Cross-Reference CK133/DRCG Pin Name PCICLK 3V66 48 MHz CPUCLK CPU_div2 APIC Clk/ClkB1 CFM/CFM#1,2 PclkM SynclkN Component PCI Slot PCI Slot PCI Slot PCI Slot PCI Slot ICH LPC Super I/O FWH Flash BIOS MCH ICH AGP Connector (on-board device) ICH
  • Intel VC820 | Design Guide - Page 134
    the 2.5V plane extends near the DRCG. However, if a 2.5V trace must be used, it should originate at the CK133 and be routed as shown. 4-6 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 135
    to RIMM (B) = RIMM to RIMM for Clocks (C) = RIMM to Termination (D) = DRCG to RIMM CFM/CFM# CTM/CTM# RIMM_0 RIMM_1 MCH 0"-3.50" A 0.4"-0.45" B 0"-3" C 0"-6" D Term DRCG b lk t Intel®820 Chipset Design Guide 4-7
  • Intel VC820 | Design Guide - Page 136
    as CFM/CFM#. Table 4-4 lists the placement guidelines. Table 4-4. Placement Guidelines for Motherboard Routing Lengths Direct Rambus* Clock Routing Length Guidelines Clock CTM/CTM# CFM/CFM# From length of every RSL signal. Exact length matching is preferred. 4-8 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 137
    as shown in Figure 4-8. Figure 4-8. Termination for Direct Rambus* Clocking Signals CFM/CFM# CFM R1 28 Ω 2% or 27 Ω 1% CFM# R2 28 Ω 2% or 27 Ω 1% C1 0 .1 uF Intel®820 Chipset Design Guide 4-9
  • Intel VC820 | Design Guide - Page 138
    required to match the impedance of the DRCG to the 28 Ω channel impedance. More detailed information can be found in the Direct Rambus Clock Generator Specification. 4-10 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 139
    resistor stubs within 250 mils of the CK133. If routing rules allow, Rpacks can be used if power dissipation is not exceeded for the Rpack. Intel®820 Chipset Design Guide 4-11
  • Intel VC820 | Design Guide - Page 140
    However, pads should be placed on the board for these external capacitors for testing/debug. Table and Jitter Specification To allow additional flexibility in board design, Intel has enabled 300 MHz (not supported by the Intel® 820 chipset). Support for 300 MHz and 400 MHz memory bus is unchanged.
  • Intel VC820 | Design Guide - Page 141
    . Output Frequency (MHz) 400 356 300 266 Component Jitter Specification 50 ps 60 ps 70 ps 80 ps Channel Jitter Guidelines in Figure 4-11. This allows selection of all frequencies supported by the Intel® 820 chipset. Figure 4-11. DRCG+ Frequency Selection U? Intel®820 Chipset Design Guide 4-13
  • Intel VC820 | Design Guide - Page 142
    Clocking This page is intentionally left blank. 4-14 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 143
    5 System Manufacturing
  • Intel VC820 | Design Guide - Page 144
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  • Intel VC820 | Design Guide - Page 145
    the FWH Flash BIOS only supports 12V Vpp for 80 hours. The 12V Vpp would be useful in a programmer environment that is typically an event that occurs very infrequently (much less than 80 hours). The VPP pin MUST be tied to 3.3V on the motherboard. Stackup Requirement Overview The Intel® 820 chipset
  • Intel VC820 | Design Guide - Page 146
    with cross-section • Adjust design parameters and/or material as required • Build a new board, re-measure the key parameters and be prepared to generate one or two board iterations This process will require iteration: design, build, test, modify, build, test... 5-2 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 147
    = Memory section of the motherboard Any section of the motherboard Separate location in the panel The Intel Impedance Test Methodology Document should be used to ensure boards are within 5-2 shows examples of both Stripline and Microstrip cross sections. Intel®820 Chipset Design Guide 5-3
  • Intel VC820 | Design Guide - Page 148
    4.5 4.5 4.5 Z0(3D) 29.0 28.4 27.6 30.4 30.2 27.9 Z0(zcalc) 29.1 28.7 27.7 30.4 30.2 28.0 5.3.8 Testing Board Impedance The Intel Impedance Test Methodology Document should be used to ensure boards are within the 28 Ω ±10% requirement. This document can be found at: http://developer
  • Intel VC820 | Design Guide - Page 149
    System Manufacturing 5.3.9 Board Impedance/Stackup Summary 1. 7628 Cloth, 1 ply 0.007" when cured with 40% resin is the most popular and Cu ~48 Mil Core Ground Layer 3: 1 oz Cu 4.5 Mil Prepreg Solder Side Layer 4: 1/2 oz Cu Total Thickness = 62 mils 4 5 il t k d Intel®820 Chipset Design Guide 5-5
  • Intel VC820 | Design Guide - Page 150
    System Manufacturing This page is intentionally left blank. 5-6 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 151
    6 System Design Considerations
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  • Intel VC820 | Design Guide - Page 153
    memory and all unnecessary system logic is turned off. Only main memory and logic required to wake the system remain powered. This state is used in the Reference Board on the motherboard. The customer reference board supports two suspend states: Suspend-to-RAM (S3) Intel®820 Chipset Design Guide 6-1
  • Intel VC820 | Design Guide - Page 154
    Intel® 820 Chipset Reference Board. This power delivery architecture supports the "Instantly Available PC Design Guidelines" via the suspend-to-RAM (STR) state. During STR, only the necessary devices are powered. These devices include: main memory S0, S1, S3, S5 FWH Flash BIOS Core: 3.3V 67mA S0, S1
  • Intel VC820 | Design Guide - Page 155
    In addition to the power planes provided by the ATX power supply, an instantly available Intel® 820 chipset based system (using Suspend-to-RAM) requires 7 power planes to be generated on the board. The requirements for each power plane are documented in this section. In addition to onboard
  • Intel VC820 | Design Guide - Page 156
    Design Considerations The Intel® 820 Chipset Reference Board is using a Specification Revision 2.0 (http://www.agpforum.org). Note: This regulator is required in ALL designs (unless the design does not support 1.5V AGP, and therefore does not support state. 6-4 Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 157
    card. Therefore, the total current requirement is: • Full-power Operation: 375 mA * number of PCI slots • Suspend Operation: 375+20 * (number of PCI slots Intel® 820 chipset based system that does not support Suspendto-RAM the initialization of memory. The amount Intel®820 Chipset Design Guide 6-5
  • Intel VC820 | Design Guide - Page 158
    For details on this DRCG mode, refer to the latest DRCG specification. By slowing down the DRCG output clock, the power consumption from is reduced. After the SetR/ClrR commands have been issued, the BIOS drives the GPO low to bring the DRCG back to normal operation. Intel®820 Chipset Design Guide
  • Intel VC820 | Design Guide - Page 159
    the power plane splits on an Intel® 820 chipset platform. Figure 6-4. by a power virus. Refer to the Intel® 820 Chipset Application Note: Thermal Design Considerations and the ICH are listed in Table 6-1. Table 6-1. Intel® 820 Chipset Component Thermal Design Power Component Thermal Design Power
  • Intel VC820 | Design Guide - Page 160
    # generation • Backfeed cutoff circuit for suspend to RAM • 5V reference generation • Flash FLUSH# / INIT# circuit • HD single color LED driver • IDE reset signal generation/PCIRST# buffers • Voltage translation for Audio MIDI signal • Audio-disable circuit • Voltage translation for DDC to monitor
  • Intel VC820 | Design Guide - Page 161
    A Reference Board Schematics: Uni-Processor
  • Intel VC820 | Design Guide - Page 162
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  • Intel VC820 | Design Guide - Page 163
    A A.1 Reference Design Feature Set The reference schematics feature the following core feature set: • Intel® 820 Chipset - Memory Controller Hub (MCH) - I/O Controller Hub (ICH) - FWH Flash BIOS Interface • Support for the Pentium III (SC242) Processor - 100/133 MHz System Bus Frequency - Debug
  • Intel VC820 | Design Guide - Page 164
    1 INTEL(R) 820 CHIPSET UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS REV F (2 RIMM) D Title Cover Sheet Block Diagram Processor Connector Clock Synthesizer MCH ICH FWH C RIMM Sockets Super I/O A udio Audio/Modem Riser LAN Sy s tem A GP Connector PCI Connectors IDE Connectors B USB Connectors Parallel
  • Intel VC820 | Design Guide - Page 165
    IDE Primary UltraDMA/66 IDE Secondary PCI CNTRL USB Port 1 USB ICH PCI ADDR/DATA USB Port 2 LPC Bus AC'97 Audio Modem AC'97 Link B FWH 82559 LAN SIO 12 ADM1021 3 B TPS2042 23 A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: BLOCK DIAGRAM 1.01 R PCD PLATFORM DESIGN
  • Intel VC820 | Design Guide - Page 166
    Edge Contact Cartridge 2 Thermal Validation" document for further details. Place R121,R122 very close to processor. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630
  • Intel VC820 | Design Guide - Page 167
    32 IGNNE# A8 IGNNE# 8,32 IERR# A4 BERR# A77 AERR# B118 RES0 A16 RES1 B20 RES2 B112 RES3 A113 A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED
  • Intel VC820 | Design Guide - Page 168
    C205 A All jumpers may not be required, but are included for test purposes. 8 7 6 No stuff R161, JP11. 5 4 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: CLOCK SYNTHESIZER 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST
  • Intel VC820 | Design Guide - Page 169
    ,21,22 MCH_HLCOMP A GRCOMP R129 40.2-1% Place R129 and R180 less than 0.5" from MCH using 10 mil trace. 5 4 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: MCH 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET
  • Intel VC820 | Design Guide - Page 170
    R19 AD_STB#1 Y20 SB_STB Y19 SB_STB# AGP 7 6 5 4 3 2 1 HUB MEMORY AGP HL0 F19 HL1 F18 HL2 E17 HL3 E19 HL4 B20 HL5 B19 HL6 B18 HL7 SBA[7:0] 11 19 Q9 C 3 B1 2 E A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD MCH R PCD PLATFORM DESIGN DRAWN BY: 1900 PRAIRIE CITY ROAD FOLSOM
  • Intel VC820 | Design Guide - Page 171
    21,32 16,32 32 21,32 C218 0.1UF Place HUBREF circuit between MCH and ICH HUBREF voltage = 0.9V +/- 2% A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: ICH 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-24
  • Intel VC820 | Design Guide - Page 172
    USBP1+ P2 USBP1P1 USBP0+ N2 USBP0M4 OC1# M3 OC0# SYSTEM AC97 GPIO LPC USB ICH_B AC_SDATAOUT 9,13,15 8 7 6 5 4 3 VCC5_REF PDCS1# N12 SDCS1# VCC5 +A -C D 22 22 C 22 B 22 A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: ICH 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT:
  • Intel VC820 | Design Guide - Page 173
    1UF LFRAME#/FWH4 HINIT# 9,12 4,8,32 LAD3/FWH3 9,12 LAD2/FWH2 9,12 LAD1/FWH1 9,12 LAD0/FWH0 9,12 1 D C B A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: FWH 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET
  • Intel VC820 | Design Guide - Page 174
    11,32 SMBCLK_CORE SMBDATA_CORE RAMREF 6,11 C256 0.1UF C243 0.1UF C236 0.1UF 1 D C B A R228 4.7K Do not stuff R228 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: RIMM SOCKETS 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST
  • Intel VC820 | Design Guide - Page 175
    Pulldown on SYSOPT for IO address of 0x02E A 4.7K 7 GND1 31 GND2 60 GND3 76 GND4 40 AVSS R312 5 4 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: SUPER I/O 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11
  • Intel VC820 | Design Guide - Page 176
    +C9 10UF-TANT 0.1UF C20 1UF-TANT +C1 270PF-NPO C18 1UF-TANT +C7 270PF-NPO C19 0.047UF AGND AGND TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: AUDIO 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-18
  • Intel VC820 | Design Guide - Page 177
    + 13 1UF C58 CD_REF_C 2 1 CD_REF + 13 1UF C50 CD_R_C 2 1 CD_R + 13 1UF AGND AGND AGND 8 7 6 5 4 A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: AUDIO 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED
  • Intel VC820 | Design Guide - Page 178
    A7 B8 GND[1] USB_OC A8 B9 +12V B10 GND[2] GND[8] A9 USB+ A10 B11 +5VD AC'97_RISER USB- A11 KEY KEY B12 GND[3] B13 RESV[3] B14 RESV[4] AMR_CONNECTOR KEY 13 1 D C B A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: AUDIO/MODEM RISER 1.01 R PCD PLATFORM DESIGN DRAWN
  • Intel VC820 | Design Guide - Page 179
    #_LAN TEST_LAN 3.3K R11 62K R14 3.3K RBIAS10 B14 RBIAS100 B13 VREF C12 RBIAS10 RBIAS100 R16 549 R15 619 A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: LAN CONTROLLER 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED
  • Intel VC820 | Design Guide - Page 180
    J17 B C5 E nable* 1-2 B No stuff C5. C5 must be rated at 1500V. 470PF No stuff C31. Dis able 2-3 A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: LAN 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: 11-18
  • Intel VC820 | Design Guide - Page 181
    1 Onboard LED indicates the standby well is on to prevent hot swapping memory. For debug only. C322 14 0.1UF R326 4.7K VCC3_3SBY VCC3_3SBY VCC3_3SBY inputs. GPIO26_FPLED 9 GND SN74LVC07A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: SYSTEM 1.01 R PCD PLATFORM DESIGN
  • Intel VC820 | Design Guide - Page 182
    AD1 6 MCH_AGPREF B66 VREF_CG J13 AGP4XU_20 12V A1 A2 TYPEDET# RESV_A A3 USB- A4 A5 GND_A INTA# A6 RST# A7 GNT# A8 VCC3_3_A A9 ST1 7,32 GAD6 GAD4 GAD2 GAD0 3 CONN_AGPREF 6 A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD AGP CONNECTOR R PCD PLATFORM DESIGN DRAWN BY: 1900 PRAIRIE
  • Intel VC820 | Design Guide - Page 183
    # PERR# SERR# C_BE#1 AD14 AD12 AD10 PCI Slot 1 J9 PCI3_CON B1 A1 B2 A2 B3 A3 VCC12 VCC5 2 1 For pullups, see 4.3.3 of PCI 2.1 Specification PTRST# PTMS 20,21 PTDI 20,21 20,21 VCC5 D A PU2_REQ64# 20 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: PCI CONNECTORS 1 AND
  • Intel VC820 | Design Guide - Page 184
    key key 6 5 4 3 2 1 VCC3_3 VCC3_3 VCC3_3 VCC5 VCC12 VCC12- VCC5 PCI Slot 3 J11 PCI3_CON VCC5 VCC12 J9 must be furthest from the processor. PTRST# 20,21 A60 B61 A61 PU4_REQ64# 21 B62 A62 TITLE: INTEL(R) 820 CHIPSET - FCPGA REFERENCE BOARD REV: PCI CONNECTORS 3 AND 4 1.0 R
  • Intel VC820 | Design Guide - Page 185
    no stuff C329,C318. P66DETECT and S66DETECT can be connected to a GPI for BIOS cable detection. VCC3_3 B 6,8,10,11,12,16,19,20,21 14 R351 VCC3_3 6 7 GND SN74LVC07A PCIRST_BUF# 22 A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: IDE CONNECTORS 1.01 R PCD PLATFORM DESIGN
  • Intel VC820 | Design Guide - Page 186
    8 7 6 5 4 3 2 1 USB Connectors VCC3_3 R83 330K D AC97_OC# 15 Do Not Stuff R82 0K VCC3_3 Not Stuff 1 C37 470PF 2 L6 USBAGP+ A 19 USBAGP19 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: USB CONNECTORS 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY
  • Intel VC820 | Design Guide - Page 187
    CP3 27 8 180PF 45 180PF 6 180PF 2 CP2 180PF C81 4 CP2 CP5 CP5 CP4 CP4 CP3 CP3 7 180PF 5 180PF A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: PARALLEL PORT 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED
  • Intel VC820 | Design Guide - Page 188
    4 CP7 3 CP7 5 100PF 7 100PF 5 100PF 2 CP7 6 100PF 6 100PF 4 CP6 1 CP7 2 CP6 8 100PF 7 100PF 3 CP6 8 100PF 1 CP6 A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: SERIAL PORTS 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST
  • Intel VC820 | Design Guide - Page 189
    16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 1 D C B A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: KEYBOARD/MOUSE/FLOPPY 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET
  • Intel VC820 | Design Guide - Page 190
    47PF 50V Tie game port capacitors together and to SIO AVSS. Tie to system ground at only a single point. A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: GAME PORT 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET
  • Intel VC820 | Design Guide - Page 191
    VRM8.4 spec . 5 4 VCC12 L19 1UH R71 5.1-5% C97 + 1UF-X7R VCC5 D PVCC_R 1 2 DO3316P-102 Place caps next to output FETs. C82,C87,C107,C111 must support > B 2 2 2 2 Sanyo 4SP2200M A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: VRM 8.2 1.01 R PCD PLATFORM DESIGN DRAWN
  • Intel VC820 | Design Guide - Page 192
    1UF-X7R C319 + 100UF R309 131-1% Place C311 at regulator. Place C108 and C333 at RIMM termination 8 7 6 5 4 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: VOLTAGE REGULATORS 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST
  • Intel VC820 | Design Guide - Page 193
    SENSE- 7 R301 100-1% VCC2_5SBY Do not stuff C304. C304 C R302 11K + 1 C325 2 + 1 C326 T510 2 R294 10K B A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: VOLTAGE REGULATORS 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630
  • Intel VC820 | Design Guide - Page 194
    using a 22 msec delay and Schmitt trigger logic. 5 4 R288 1M RSMRST# 9,17 No stuff. For test only A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: POWER CONNECTOR 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED
  • Intel VC820 | Design Guide - Page 195
    7,19 ST1 8.2K R506 7,19 ST2 R507 8.2K 7,19 8.2K B ADSTB#0 R207 7,19 ADSTB#1 8.2K R136 7,19 8.2K A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: PCI/AGP PULLUPS/PULLDOWNS 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630
  • Intel VC820 | Design Guide - Page 196
    0 ohm resistors. VCC1_8 TERM_CMD 11 TERM_SCK 11 R292 39.2-1% R290 39.2-1% 90.9-1% R293 90.9-1% R291 1 D C B A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: RAMBUS TERMINATION 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630
  • Intel VC820 | Design Guide - Page 197
    7 GND U20 14VCC 13 12 A Place VDDQ capacitors within SN74LVC06A7 GND 70 mils of outer balls of MCH. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: DECOUPLING 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET
  • Intel VC820 | Design Guide - Page 198
    Decoupling VTT1_5 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF Place caps at VTT pins on Slot 1 connector. 5 4 B A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: BULK DECOUPLING 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA
  • Intel VC820 | Design Guide - Page 199
    for RIMM connectors. Added solder side decoup for MCH. Changed VDDQ cap values from 0.1uF to 0.01uF. C 1 D C B B A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: REVISION HISTORY 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630
  • Intel VC820 | Design Guide - Page 200
    HL3 7,8 HL9 7,8 HL_STB 7,8 HL_STB# 7,8 HL10 7,8 HL8 7,8 HL4 7,8 HL5 7,8 HL6 7,8 VCC1_8 B HL7 7,8 P08-050-SL-A-G 1 D C B A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST
  • Intel VC820 | Design Guide - Page 201
    B Reference Board Schematics: Dual-Processor
  • Intel VC820 | Design Guide - Page 202
    This page is intentionally left blank.
  • Intel VC820 | Design Guide - Page 203
    B B.1 Reference Design Feature Set The reference schematics feature the following core feature set: • Intel® 820 Chipset - Memory Controller Hub (MCH) - I/O Controller Hub (ICH) - FWH Flash BIOS interface • Support for the two Pentium III (SC242) Processors - 100/133 MHz System Bus Frequency
  • Intel VC820 | Design Guide - Page 204
    to r s USB Connec tors B specifications and product descriptions at any time, without notice. 34 Copyright © Intel Corporation 1999. 35 36, 37 *Third-party brands and names are the property of their respective owners. A 38 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
  • Intel VC820 | Design Guide - Page 205
    C IDE Primary UltraDMA/66 IDE Secondary USB Port 1 USB Port 2 USB ICH PCI CNTRL PCI ADDR/DATA AC'97 Audio Modem AC'97 Link B FWH 82559 LAN SIO 3 ADM1021 5 TPS2042 25 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: BLOCK DIAGRAM 3.03 R PCD PLATFORM
  • Intel VC820 | Design Guide - Page 206
    Contact Cartridge 2 Thermal Validation" document for further details. Place R19, R100 very close to processor. TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA
  • Intel VC820 | Design Guide - Page 207
    # A8 IGNNE# 6,10,34 IERR# A4 BERR# A77 AERR# B118 RES0 A16 RES1 B20 RES2 B112 RES3 A113 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST
  • Intel VC820 | Design Guide - Page 208
    Contact Cartridge 2 Thermal Validation" document for further details. Place R121, R122 very close to processor. TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA
  • Intel VC820 | Design Guide - Page 209
    ,34 B 4,10,34 4,10,34 4,10,34 4,10,34 4,10,34 4,10,12,34 4,10,34 4,10,34 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET
  • Intel VC820 | Design Guide - Page 210
    VDDIPD 10 VDDO1 16 VDDO2 22 VDDP 3 VDDC 9 R219 10K R204 10K R199 10K B HOST BUS /RAM BUS JP 13 100/300 2 -3 100/400 OUT 133/400 2 -3 G P O CNTRL* 1 # 13 No stuff C80 C205 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: CLOCK SYNTHESIZER 3.03 R PCD PLATFORM
  • Intel VC820 | Design Guide - Page 211
    MCH_HLCOMP A GRCOMP R129 40.2-1% Place R129 and R180 less than 0.5" from MCH using 10 mil trace. 5 4 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: MCH 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED
  • Intel VC820 | Design Guide - Page 212
    AD_STB1 R19 AD_STB#1 Y20 SB_STB Y19 SB_STB# AGP 7 6 5 4 3 2 1 HUB MEMORY AGP HL0 F19 HL1 F18 HL2 E17 HL3 E19 HL4 B20 HL5 B19 HL6 B18 HL7 A20 13 21 Q9 C 3 B1 2 E A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: MCH 3.03 R PCD PLATFORM DESIGN DRAWN BY:
  • Intel VC820 | Design Guide - Page 213
    18,34 34 23,34 C218 0.1UF Place HUBREF circuit between MCH and ICH A HUBREF voltage = 0.9V +/- 2% TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: ICH 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET
  • Intel VC820 | Design Guide - Page 214
    R1 USBP1+ P2 USBP1P1 USBP0+ N2 USBP0M4 OC1# M3 OC0# SYSTEM AC97 GPIO LPC USB ICH_B AC_SDATAOUT 11,15,17 8 7 6 5 4 3 VCC5_REF PDCS1# N12 SDCS1 -C D 24 24 C 24 B 24 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: ICH 3.03 R PCD PLATFORM DESIGN DRAWN BY:
  • Intel VC820 | Design Guide - Page 215
    ,14 4,6,10,34 LAD3/FWH3 LAD2/FWH2 LAD1/FWH1 LAD0/FWH0 11,14 11,14 11,14 11,14 1 D C B A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: FWH 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11
  • Intel VC820 | Design Guide - Page 216
    SWP C169 0.1UF C256 0.1UF C243 0.1UF C236 0.1UF A R152 10K 1 D C B A R228 4.7K Do not stuff R228 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: RIMM SOCKETS 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST
  • Intel VC820 | Design Guide - Page 217
    on SYSOPT for IO address of 0x02E A 4.7K 7 GND1 31 GND2 60 GND3 76 GND4 40 AVSS R312 5 4 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: SUPER I/O 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET
  • Intel VC820 | Design Guide - Page 218
    047UF C17 1UF-TANT +C1 1 C18 1 +C7 2 270PF-NPO 2 1UF-TANT 270PF-NPO C19 A A 2 AGND AGND TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: AUDIO 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET
  • Intel VC820 | Design Guide - Page 219
    15 1UF C50 CD_R_C 2 1 CD_R + 15 1UF R51 4.7K R30 4.7K R25 4.7K AGND AGND AGND 8 7 6 5 4 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: AUDIO 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED
  • Intel VC820 | Design Guide - Page 220
    A7 B8 GND[1] USB_OC A8 B9 +12V B10 GND[2] GND[8] A9 USB+ A10 B11 +5VD AC'97_RISER USB- A11 KEY KEY B12 GND[3] B13 RESV[3] B14 RESV[4] AMR_CONNECTOR KEY D C B A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: AUDIO/MODEM RISER 3.03 R PCD PLATFORM DESIGN
  • Intel VC820 | Design Guide - Page 221
    TEST_LAN 3.3K R363 62K R14 3.3K RBIAS10 B14 RBIAS100 B13 VREF C12 RBIAS10 RBIAS100 R16 549 R15 619 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: LAN CONTROLLER 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST
  • Intel VC820 | Design Guide - Page 222
    C5 No stuff C5. Enable* 1-2 B 470PF C5 must be rated at 1500V. No stuff C31. Disable 2-3 A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: LAN 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: 11
  • Intel VC820 | Design Guide - Page 223
    1 Onboard LED indicates the standby well is on to prevent hot swapping memory. For debug only. C322 14 0.1UF R326 4.7K VCC3_3SBY VCC3_3SBY VCC3_3SBY VCC3_3SBY inputs. GPIO26_FPLED11 GND SN74LVC07A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: SYSTEM 3.03 R PCD
  • Intel VC820 | Design Guide - Page 224
    9 GC/BE#[3:0] VCC5 J13 25 AGP_OC# B1 OVRCNT# B2 5V_A B3 5V_B USBAGP+ B4 25 USB+ B5 GND_K B6 INTB# AGPCLK_CONN B7 CLK 9,34 GREQ# B8 REQ# B9 VCC3_3_F ST0 B10 GAD0 3 CONN_AGPREF 8 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: AGP CONNECTOR 3.03 R
  • Intel VC820 | Design Guide - Page 225
    PERR# SERR# C_BE#1 AD14 AD12 AD10 PCI Slot 1 J11 PCI3_CON B1 A1 B2 A2 B3 A3 VCC12 VCC5 2 1 For pullups, see 4.3.3 of PCI 2.1 Specification PTRST# PTMS 22,23 PTDI 22,23 22,23 VCC5 PU2_REQ64# 22 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PCI CONNECTORS 1
  • Intel VC820 | Design Guide - Page 226
    key key 6 5 4 3 2 1 VCC3_3 VCC3_3 VCC3_3 VCC5 VCC12 VCC12- VCC5 PCI Slot 3 J9 PCI3_CON VCC5 VCC12 J9 must be furthest from the processor. PTRST# 22,23 A61 PU4_REQ64# 23 B62 A62 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PCI CONNECTORS 3 AND 4 3.03
  • Intel VC820 | Design Guide - Page 227
    , no stuff C329,C318. P66DETECT and S66DETECT can be connected to a GPI for BIOS cable detection. VCC3_3 B 8,10,12,13,14,18,21,22,23 14 R351 7 GND SN74LVC07A PCIRST_BUF# 24 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: IDE CONNECTORS 3.03 R PCD PLATFORM
  • Intel VC820 | Design Guide - Page 228
    USBD1N 0K R44 USBD1P 0K USBG1 Do Not Stuff 1 C37 470PF 2 L6 USBAGP+ A 21 USBAGP21 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: USB CONNECTORS 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED
  • Intel VC820 | Design Guide - Page 229
    27 8 180PF 45 180PF 6 180PF 2 CP2 180PF C81 4 CP2 CP5 CP5 CP4 CP4 CP3 CP3 7 180PF 5 180PF A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PARALLEL PORT 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST
  • Intel VC820 | Design Guide - Page 230
    3 CP7 5 100PF 7 100PF 5 100PF 2 CP7 6 100PF 6 100PF 4 CP6 1 CP7 2 CP6 8 100PF 7 100PF 3 CP6 8 100PF 1 CP6 A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: SERIAL PORTS 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630
  • Intel VC820 | Design Guide - Page 231
    15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 1 D C B A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: KEYBOARD/MOUSE/FLOPPY 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED
  • Intel VC820 | Design Guide - Page 232
    Tie game port capacitors together and to SIO AVSS. Tie to system ground at only a single point. A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: GAME PORT 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED
  • Intel VC820 | Design Guide - Page 233
    on VRM8.4 spec . 5 4 VCC12 L19 1UH R71 5.1-5% C97 + 1UF-X7R VCC5 D PVCC_R 1 2 DO3316P-102 Place caps next to output FETs. C82,C87,C107,C111 must support >6A JP16 JP27 JP29 JP28 JP30 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: VRM 3.03 R PCD PLATFORM DESIGN
  • Intel VC820 | Design Guide - Page 234
    R133 100-1% 1UF-X7R 100UF R309 131-1% 2 2 Place C311 at regulator. Place C108, C333 at RIMMs 8 7 6 5 4 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: VOLTAGE REGULATORS 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA
  • Intel VC820 | Design Guide - Page 235
    + VCC2_5SBY_SENSEVCC2_5SBY_VOSENSE VCC2_5SBY Do not stuff C292. B B VCMOS1_8SBY R259 35.7-1% C263 R258 100-1% 0.1UF A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: VOLTAGE REGULATORS 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD
  • Intel VC820 | Design Guide - Page 236
    ,19 No stuff. For test only A Resume Reset circuitry using a 22 msec delay and Schmitt trigger logic. TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: POWER CONNECTOR 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST
  • Intel VC820 | Design Guide - Page 237
    8.2K R384 8.2K R198 8.2K R385 8.2K R394 8.2K ADSTB#0 R207 B 9,21 ADSTB#1 8.2K R136 9,21 8.2K A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PCI/AGP PULLUPS/PULLDOWNS 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA
  • Intel VC820 | Design Guide - Page 238
    two RSL signals. 3 2 VCC1_8 TERM_CMD 13 TERM_SCK 13 R292 39.2-1% R290 39.2-1% 90.9-1% R293 90.9-1% R291 1 D C B A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: RAMBUS TERMINATION 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM
  • Intel VC820 | Design Guide - Page 239
    7 GND SN74LVC07A U19 VCC 14 11 10 7 GND SN74LVC07A U19 VCC 14 13 12 7 GND SN74LVC07A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: DECOUPLING 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED
  • Intel VC820 | Design Guide - Page 240
    + 22UF C367 2 1 + 22UF Place caps at VTT pins on Slot 1 connector. VCCVID Core Voltage Decoupling VCCVID VCCVID1 VCCVID1 VCC3_3SBY B 0.1UF C149 C150 C151 C152 C153 A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: BULK DECOUPLING 3.03 R PCD PLATFORM
  • Intel VC820 | Design Guide - Page 241
    . Added solder side decoup for MCH. Changed VDDQ cap values from 0.1uF to 0.01uF. C 3 2 1 D C B B A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: REVISION HISTORY 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630
  • Intel VC820 | Design Guide - Page 242
    Robert Noyce Building 2200 Mission College Boulevard P.O. Box 58119 Santa Clara, CA 95052-8119 USA Phone: (800) 628-8686 Europe Intel Corporation (UK) Ltd. Pipers Way Swindon Wiltshire SN3 1RJ UK Phone: England (44) 1793 403 000 Germany (49) 89 99143 0 France (33) 1 4571 7171 Italy
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Intel
®
820 Chipset
Design Guide
July 2000
Order Number:
290631-004