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Intel VC820 Design Guide - Page 207

CPU TACH0, Single CPU0, Dual CPU

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8 7 6 Processor Connector 0 D ITP VCC3_3 VCC2_5 VTT1_5 VCC2_5 5 VTT1_5 4 VTT1_5 VCCVID J15 R159 R17 240 1K R63 1K R18 1K R387 330 R76 330 R380 R218 150 150 R94 240 R386 240 R11 47 R7 47 ITP_PU_R 4,6,8CPURST# R95 CPURST#_R C 33 DBRESET# 240 TMS_R 6 TCK_R XREF=6 ITPCLK 7 J26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 B VCC12 R7 and R11 should be placed within 1" of ITP connector. R93 680 TRST# 6 ITPREQ# 4 ITPRDY#_R ITPREQ1# 6 ITPRDY1#_R ITPPRDY# ITPRDY1# TCK 6 TMS R2 0K R1 0K 0.1UF CPU TACH0 C36 JP31 1 2 3 A VCC2_5 ITP Config Single CPU0 Dual CPU Single CPU1 JP33 1-2 2-3 2-3 JP34 1-2 1-2 2-3 R3 0K VCC3_3 TDI 4 TDO 4 R376 6 4 33 6 6,10,34 6,10,34 7 SLOTOCC0# 4 4,6 8.2K BINIT# PICD0 PICD1 PICCLK TDI_0 TDO_0 A25 DEP#0 A27 DEP#1 B26 DEP#2 A28 DEP#3 B27 DEP#4 A29 DEP#5 A31 DEP#6 B28 DEP#7 B19 BP2# A21 BP3# A23 BPM0# B24 BPM1# A24 BINIT# A19 PICD0 B22 PICD1 B18 PICCLK B101 A9 A11 B11 B7 B10 SLOTOCC# TDI TDO TRST# TCK TMS EMI1 EMI2 EMI3 EMI4 EMI5 B61 B100 B81 B1 B41 EMI_1 EMI_2 EMI_3 EMI_4 EMI_5 0K R4 6,7 6,33 4,6,8 CPUHCLK PWRGOOD CPURST# A75 BCLK A12 PWRGOOD B74 RESET# VCC2_5 0K 330 R5 R388 R92 150 R64 150 4,6 TDO_0 6 TDO_1 JP33 1 2 3 TDO 4 4 TDI JP34 1 2 3 TDI_0 4 8 7 6 5 4 GND29 A118 GND28 A114 GND27 A110 GND26 A106 GND25 A102 GND24 A98 GND23 A94 GND22 A90 GND21 A86 GND20 A82 GND19 A78 GND18 A74 GND17 A70 GND16 A66 GND15 A62 GND14 A58 GND13 A54 GND12 A50 GND11 A46 GND10 A42 GND9 A38 GND8 A34 GND7 A30 GND6 A26 GND5 A22 GND4 A18 GND2 A10 GND1 A6 GND0 A2 B121 VCC3_3 B117 VCC3_2 B113 VCC3_1 B109 VCC5 B105 VCCP19 B97 VCCP18 B93 VCCP17 B89 VCCP16 B85 VCCP15 B77 VCCP14 B73 VCCP13 B69 VCCP12 B65 VCCP11 B57 VCCP10 B53 VCCP9 B49 VCCP8 B45 VCCP7 B37 VCCP6 B33 VCCP5 B29 VCCP4 B25 VCCP3 B17 VCCP2 B13 VCCP1 B9 VTT4 B5 VTT3 A3 VTT2 A1 VTT1 3 2 VCC5 VCC3_3 1 D SC242 AP0# AP1# BNR# BPRI# TRDY# DEFER# LOCK# DRDY# HITM# HIT# DBSY# HADS# A117 B116 A101 A103 A104 A105 B106 B107 A109 B110 A111 A115 BNR# BPRI# HTRDY# DEFER# HLOCK# DRDY# HITM# HIT# DBSY# HADS# 6,8 6,8 6,8 6,8 6,8 6,8 6,8 C 6,8 6,8 VCC3_3 6,8 PREQ# A20 PRDY# B23 BREQ0# A76 BREQ1# B75 RES4 B76 TESTHI A13 BSEL0 BSEL1 B21 A14 FLUSH# B2 ITPREQ# ITPPRDY# BREQ#0 BREQ#1 TESTHI SEL133/100# FLUSH# 4 4 R375 6 6 220 34 6,7,9 6,34 THMTRP# A15 A20M# A5 A20M# STPCLK# B6 STPCLK# 6,10,34 B 6,10,34 SLP# B8 SLP# 6,10,34 SMI# B3 SMI# 6,10,34 LINT0 A17 LINT0 6,10,34 LINT1 B16 LINT1 6,10,34 INIT# B4 HINIT# 6,10,12,34 FERR# A7 FERR# 6,10,34 IGNNE# A8 IGNNE# 6,10,34 IERR# A4 BERR# A77 AERR# B118 RES0 A16 RES1 B20 RES2 B112 RES3 A113 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-29-1999_14:45 4 OF 38 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-29-1999_14:45

PROCESSOR CONNECTOR

ITPPRDY#

150

R380

BINIT#

6,10,34

PICD0

6,10,34

PICD1

PICCLK

SLOTOCC0#

TDI_0

4,6

TDO_0

6,10,34

IGNNE#

6,10,34

FERR#

6,10,12,34

HINIT#

6,10,34

LINT1

6,10,34

LINT0

6,10,34

SMI#

6,10,34

SLP#

6,10,34

STPCLK#

6,10,34

A20M#

6,34

FLUSH#

6,7,9

SEL133/100#

TESTHI

BREQ#1

BREQ#0

ITPPRDY#

ITPREQ#

6,8

HADS#

6,8

DBSY#

6,8

HIT#

6,8

HITM#

6,8

DRDY#

6,8

HLOCK#

6,8

DEFER#

6,8

HTRDY#

TCK

TMS

EMI1

EMI2

EMI3

EMI4

EMI5

6,7

CPUHCLK

6,33

PWRGOOD

4,6,8

CPURST#

6,8

BPRI#

6,8

BNR#

R92

150

JP34

JP33

ITPREQ1#

330

R387

R386

240

ITPRDY#_R

TMS_R

ITPCLK

CPURST#_R

CPURST#

4,6,8

DBRESET#

XREF=6

TCK_R

ITP_PU_R

240

R95

R11

680

R93

240

R159

R17

R63

R18

J26

8.2K

R376

220

R375

0.1UF

C36

JP31

R94

240

ITPREQ#

330

R76

ITPRDY1#_R

R64

150

TDO_1

330

R388

TDI_0

4,6

TDO_0

TDI

TDO

TDI

TDO

J15

B53

B49

B45

B37

B33

B29

B25

B17

B105

B97

B93

B89

B85

B77

B73

B69

B65

B57

B13

B109

B121

B117

B113

B11

A104

B10

A15

A13

A11

B101

B74

B20

B112

A113

A16

A12

A20

B23

B22

A19

B18

B106

B16

A17

A109

B110

A115

A38

A34

A30

A26

A22

A18

A14

A118

A114

A110

A106

A102

A98

A94

A90

A86

A82

A10

A78

A74

A70

A66

A62

A58

A54

A50

A46

A42

B76

B41

B81

B100

B61

B107

B28

A31

A29

B27

A28

B26

A27

A25

A105

A111

A75

B75

A76

A103

B24

A23

A21

B19

A101

A24

A77

B116

A117

B118

B21

ITPRDY1#

150

R218

TRST#

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

VTT1_5

VCC3_3

VCC2_5

VCC3_3

VCC12

VCCVID

VTT1_5

VCC5

VCC3_3

VCC2_5

VCC3_3

A20M#

AERR#

AP0#

AP1#

BERR#

BINIT#

BNR#

BP2#

BP3#

BPM0#

BPM1#

BPRI#

BREQ0#

BREQ1#

BCLK

DBSY#

DEFER#

DEP#0

DEP#1

DEP#2

DEP#3

DEP#4

DEP#5

DEP#6

DEP#7

DRDY#

EMI_1

EMI_2

EMI_3

EMI_4

EMI_5

FERR#

FLUSH#

RES4

GND0

GND1

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND18

GND19

GND2

GND20

GND21

GND22

GND23

GND24

GND25

GND26

GND27

GND28

GND29

GND4

GND5

GND6

GND7

GND8

GND9

HADS#

HIT#

HITM#

IERR#

IGNNE#

INIT#

LINT0

LINT1

LOCK#

PICCLK

PICD0

PICD1

PRDY#

PREQ#

PWRGOOD

RES0

RES3

RES2

RES1

RESET#

SLOTOCC#

SLP#

SMI#

STPCLK#

TCK

TDI

TDO

TESTHI

THMTRP#

TMS

TRDY#

TRST#

VCC3_1

VCC3_2

VCC3_3

VCC5

VCCP1

VCCP10

VCCP11

VCCP12

VCCP13

VCCP14

VCCP15

VCCP16

VCCP17

VCCP18

VCCP19

VCCP2

VCCP3

VCCP4

VCCP5

VCCP6

VCCP7

VCCP8

VCCP9

VTT1

VTT2

VTT3

VTT4

BSEL0

BSEL1

SC242

VTT1_5

R7 and R11 should be placed within 1" of ITP connector.

ITP

Processor Connector 0

CPU TACH0

ITP Config

JP33

JP34

Single CPU0

1-2

Dual CPU

2-3

1-2

Single CPU1

2-3