Intel VC820 Design Guide - Page 20
Platform Initiatives, 1.4.1 Direct Rambus*, 1.4.2 Streaming SIMD Extensions, 1.4.3 AGP 2.0
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Introduction 1.4 1.4.1 1.4.2 1.4.3 1.4.4 Platform Initiatives Direct Rambus* The Direct Rambus* (RDRAM) initiative provides the memory bandwidth necessary to obtain optimal performance from the Pentium III processor as well as a high-performance AGP graphics controller. The MCH RDRAM interface supports 266 MHz, 300 MHz, 356 MHz, and 400 MHz operation; the latter delivers 1.6 GB/s of theoretical memory bandwidth; twice the memory bandwidth of 100 MHz SDRAM systems. Coupled with the greater bandwidth, the RDRAM protocol, which is heavily pipelined, provides substantially more efficient data transfer. The RDRAM memory interface can achieve greater than 95% utilization of the 1.6 GB/s theoretical maximum bandwidth. In addition to RDRAM's performance features, the new memory architecture provides enhanced power management capabilities. The powerdown mode of operation enables Intel® 820 chipset based systems to cost-effectively support suspend-to-RAM. Streaming SIMD Extensions The Pentium III processor provides 70 new Streaming SIMD (single instruction, multiple data) Extensions. The Pentium III new extensions are floating point SIMD extensions. Intel MMX™ technology provides integer SIMD extensions. The Pentium III processor new extensions complement the Intel MMX™ technology SIMD extensions and provide a performance boost to floating-point intensive 3D applications. AGP 2.0 The AGP 2.0 interface, along with Direct Rambus* memory technology, allows graphics controllers to access main memory at over 1 GB/s; twice the AGP bandwidth of previous AGP platforms. AGP 2.0 provides the infrastructure necessary for photorealistic 3D. In conjunction with Direct Rambus* and the Pentium III processor new Streaming SIMD Extensions, AGP 2.0 delivers the next level of 3D graphics performance. Hub Interface As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become significant. With the addition of AC'97 and ATA/66, coupled with the existing USB, I/O requirements will begin to impact PCI bus performance. The Intel® 820 chipset's hub interface architecture ensures that the I/O subsystem, both PCI and the integrated I/O features (IDE, AC'97, USB, etc.), receives adequate bandwidth. By placing the I/O bridge on the hub interface instead of PCI, the hub architecture ensures that both the I/O functions integrated into the ICH and the PCI peripherals obtain the bandwidth necessary for peak performance. In addition, the hub interface's lower pin count allows a smaller package for the MCH and ICH. 1-8 Intel®820 Chipset Design Guide