Intel VC820 Design Guide - Page 132
Intel, Chipset Clock Routing Guidelines,
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Clocking Figure 4-2 shows the Intel® 820 chipset clock length routing guidelines. Figure 4-2. Intel® 820 Chipset Clock Routing Guidelines1,2 Y CPUCLK to SC242 Y CPUCLK to MCH 5.3" ±0" Note: Tie CPUCLK for the MCH to CPUCLK to the SC242 to eliminate pin-to-pin skew. 3V66 Clock for Z AGP Slot PCI Clock for Z PCI Slots 3V66 Clock for Z MCH and ICH Z PCI Clock for ICH 1.5" 4" 4" ±TBD3 ±0" ±0" PCI Clock for On-Board Z Devices (excluding ICH) 4" ±TBD3 Note: 1. Tie 3V66 clock for the MCH to 3V66 clock for the AGP connector to eliminate pin-to-pin skew. 2. These calculations based on 150ps/in trace velocity. 3. The TBD value will be derived from the PCI Revision 2.2 Specification which allows for a maximum of ±2ns clock skew. 820 lk t d 4-4 Intel®820 Chipset Design Guide