Intel VC820 Design Guide - Page 139
DRCG Layout Example, 4.4 AGP Clock Routing Guidelines
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Clocking 4.3.1 DRCG Layout Example Figure 4-10. DRCG Layout Example Cmid - 100pF EMI Cap - 4pF Do Not Stuff Rp - 51 Ω (Keep trace from Rs to Rp short) Decoupling Cap - 0.1uF (Place VERY Near DRCG 3.3V Pin!) Decoupling Cap - 0.1uF (Place VERY Near DRCG 3.3V Pin!) Ferrite Bead (L22 in Reference Schematics) CTM/CTM# route on bottom layer Rs - 39 Ω (Keep trace from DRCG to Rs VERY short) Decoupling Cap - 0.1uF (Place VERY Near DRCG 3.3V Pin!) 3.3V-DRCG Flood Flood 3.3V-DRCG on the top layer around DRCG. Flood MUST include: 4 DRCG Power Pins 4 0.1uF Capacitors 1 10uF Bulk Capacitor 1 Isolation Ferrite Bead Decoupling Cap - 0.1uF (Place VERY Near DRCG 3.3V Pin!) Bulk Decoupling Cap - 10uF (Place Near DRCG) 4.4 4.5 AGP Clock Routing Guidelines The AGP clock must be routed with 20 mil spacing to all other signals and it must meet the length guidelines in Figure 4-2. Series Termination Resistors for CK133 Clock Outputs All used outputs require series termination resistors. The recommended resistor value will be defined by simulations. The stub length to the CK133 of these resistors can be compromised to make room for decoupling caps. The rule is to keep all resistor stubs within 250 mils of the CK133. If routing rules allow, Rpacks can be used if power dissipation is not exceeded for the Rpack. Intel®820 Chipset Design Guide 4-11