Intel VC820 Design Guide - Page 172
RICH_B, No WD Reboot, Reboot on W D, Safe Mode, ICH strap, Normal, Clear
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BAT17 CR3 C15 VCC5REF L1 VCCSUS1 N1 VCCSUS G1 VCCRTC BAT17 CR4 8 ICH 7 VCC3_3SBY 6 VCC_RTC_JP +A -C VCC3_3 R245 1 D 1K R231 THRM# 3 C246 + 1UF 2 VBAT_CR CA+ CR5 R241 8.2K RTC_RST_JP JP20 1 2 3 RTC_CLR 1 VCC3_3 2 R250 VBAT_RC 12 1K C249 12 VBAT_RTC 8.2K 8.2K R254 R317 29,31 30 7,16,29,31 18 25 17,31 5,12 18 3,11,32 3,11,32 32 8.2K R232 SLP_S3# SLP_S5# PWROK PWRBTN# ICH_RI# RSMRST# MULT1_GPIO GPIO26_FPLED SMBDATA_CORE SMBCLK_CORE SMB_ALERT LPC_SMI# LPC_PME# INTRUDER# BAT17 0.047UF C247 + 2.2UF R233 1K 21 C + 8.2K RTCRST# VBIAS RTCX1 3 BAT1 Use CR2032 battery. R247 10M C250 S tra p No W D Reboot JP26 IN 12PF 12PF R249 10M Y4 XTAL 2 1 32.768KHZ C251 5 5 5 15 13,15 13,15 9,13,15 13,15 15 9,18 RTCX2 ICH_CLK66 ICH_14MHZ ICH_48MHZ AC_RST# AC_SYNC AC_BITCLK AC_SDATAOUT AC_SDATAIN0 AC_SDATAIN1 SPKR Reboot on W D* OUT R212 GPIO12 S tra p B S afe M ode ICH s trap* JP 5 IN OUT 21 PCI_TEST R98 0K 5 DRCG_CTRRL162 0K R215 8.2K 8.2K 5 18 16,32 16,32 GPIO13 GPIO21 MULT0_GPIO GPIO23_FPLED ALERTCLK_SBY ALERTDATA_SBY CM OS Norm al* Clear JP20 1-2 2-3 No stuff R98. 10,12 VCC3_3SBY 10,12 10,12 10,12 R238 12 LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LDRQ#0 GPIO8 SPKR 9,18 VCC3_3 8.2K 10,12 LFRAME#/FWH4 JP26 2.7K A SPKR_STRAP USBP1P 23 USBP1N 23 USBP0P 23 USBP0N 23 OC#1 23 OC#0 23 R341 R90 2.7K AC_SDOUT_STRAP JP5 5 U13 ICH_096 4 VCC3_3SBY D14 THRM# K3 GPIO24/SLP_S3# K2 SLP_S5# J3 PWROK M2 PWRBTN# L3 RI# F1 RSMRESET# L4 GPIO25/SUSSTAT# K4 SUSCLK/GPIO26 J1 SMBDATA J2 SMBCLK M1 GPIO11/SMBALERT# E11 GPIO6 D11 GPIO5 J4 GPIO10/INTRUDER# H1 RTCRST# H2 VBIAS H3 RTCX1 H4 RTCX2 A16 CLK66 U6 CLK14 U2 CLK48 T1 AC_RST# T3 AC_SYNC R3 AC_BIT_CLK T2 AC_SDOUT U1 ACSDIN0 P3 GPIO9/AC_SDIN1 U3 SPKR N4 GPIO12 L2 GPIO13 B14 GPIO21 D13 GPIO22 D15 GPIO23 M5 GPIO27/ALERT_CLK L5 GPIO28/ALERT_DATA R6 LAD0/FWH0 U5 LAD1/FWH1 T5 LAD2/FWH2 T4 LAD3/FWH3 T6 LDRQ0# N3 GPIO8/LDRQ1# U4 LFRAME#/FWH4 R1 USBP1+ P2 USBP1P1 USBP0+ N2 USBP0M4 OC1# M3 OC0# SYSTEM AC97 GPIO LPC USB ICH_B AC_SDATAOUT 9,13,15 8 7 6 5 4 3 VCC5_REF PDCS1# N12 SDCS1# L14 PDCS3# U13 SDCS3# L16 PDA0 PDA1 PDA2 SDA0 SDA1 SDA2 R12 T12 P12 M16 M15 L13 PDDREQ U11 SDDREQ P17 PDDACK# U12 SDDACK# M13 PDIOR# R11 SDIOR# N16 PDIOW# T11 SDIOW# N15 PIORDY N11 SIORDY N17 PDD0 R10 PDD1 N9 PDD2 R9 PDD3 U9 PDD4 R8 PDD5 U8 PDD6 R7 PDD7 U7 PDD8 P7 IDE PDD9 N7 PDD10 T8 PDD11 P8 PDD12 T9 PDD13 P9 PDD14 T10 PDD15 P10 SDD0 P15 SDD1 R16 SDD2 T17 SDD3 U16 SDD4 U15 SDD5 R14 SDD6 P13 SDD7 T13 SDD8 U14 SDD9 T14 SDD10 P14 SDD11 T15 SDD12 U17 SDD13 R15 SDD14 R17 SDD15 P16 2 1 C233 2 PDCS#1 SDCS#1 PDCS#3 SDCS#3 PDA0 PDA1 PDA2 SDA0 SDA1 SDA2 PDREQ SDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 22 22 22 22 PDA[2:0] SDA[2:0] 22 22 22 22 22 22 22 22 22 22 PDD[15:0] SDD[15:0] C234 + 1UF 0.1UF R230 1K 1 VCC3_3 VCC5 +A -C D 22 22 C 22 B 22 A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: ICH 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 12-2-1999_16:22 9 OF 36 3 2 1