Sharp CD-ES9 Service Manual - Page 81

CD-ES900/CD-ES99 IC1 VHiLC78648E-1: CD Digital Signal Processor (LC78648E) (2/2) Pin No. 44 45 46 47 48 Terminal Name RCHO RVDD XVSS XOUT XIN Input/Output Output Input - Output Input Setting in Reset RVDD /2 - - Oscillator Oscillator Function Right channel R channel Power supply pin. D/A converter R channel output supply pin. Digital GND pin. Must always be connected to 0 V Crystal oscillator Power supply for crystal oscillator. Connected for a 16.9344 MHz crystal oscillator pin. 49 XVDD 50 IOMODE Input Input 51 F16MIN 52* OUT1 53* 16MOUT Input Output Output 54 ASLRCK Input 55 ASDACK Input 56 ASDFIN Input 57* LRSK 58* DATACK 59* DATA 60 DVDD 61 DVSS 62 CE 63 CL 64 DI 65 DO 66 WRQB 67 RESB Output Output Output Input - Input Input Input Output Output Input 68 DRF 69 C2F/SBCK Output Input/Output 70 CONT6/SBCK Input/Output 71* MONI5 72* MONI4 73* MONI3 74 CONT5 75 CONT4 76 PDO1 77 PDO2 78 PCKIST 79 VVSS 80 VVDD Output Output Output Input/Output Input/Output Output Output Input - Input - - - L CLK Output - - - L L L - - - - - (H) L - L Input Input L L L Input Input - - - - - Digital power supply pin. Must always be connected to 0 V CONT4 to 6. MONI3~5, DRF, WRQB pin output mode switching input pin. "L" setting: Normal output "H" setting: Nch open drain output DF. DAC external clock input pin. General-purpose output pin 1. 16.9344 MHz output port. Left/Right clock input pin. (Must be connect to 0 V when unused.) Anti-shock Bit clock input pin. (Must be connect to 0 V when unused.) Left/Right channel data input pin. (Must be connect to 0 V when unused.) Digital data output Left/Right channel data output pin. Bit clock output pin. Left/Right clock output pin. Digital power supply pin. Digital GND pin 2. Must always be connected to 0 V. Chip enable signal input pin. Microcomputer Data transfer clock input pin. Interface Data output pin. Data output pin. (Try state output.) Interruption signal output pin. Reset input pin for LSI. This pin must be set LOW briefly after power is first applied. Focus ON detection pin. Error flag monitor pin, or sub code Controlled by commands from the micro- read clock input pin. processor. General-purpose I/O pin 6, or sub Controlled by commands from the micro- code read clock input pin. processor. Any of these that are unused must be either set up as input pin ports and connected to 0 V, or set up as output pin ports and left open. Internal signal monitor pin 5. Internal signal monitor pin 4. Internal signal monitor pin 3. General pur- Controlled by command from the microprocessor. Any of pose I/O pin 5. these that are unused must be either set up as input pin General purpose I/O pin 4. ports and connected to 0 V, or set up as output pin ports and left open when unused. Phase comparison output pin 1 to control built-in VCO. Phase comparison output pin 2 to control built-in VCO. PLL Resistor connection pin to set current for PDO1 and 02 outputs. Built-in VCO GND pin. Must always be connected to 0 V. Built-in VCO power supply pin. In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside. The same potential must be supplied to all power supply pins, i, e., AVDD1, AVDD2, XVDD, DVDD, LVDD and RVDD) 8 - 2