Sharp CD-ES9 Service Manual - Page 82

IC1 VHiLC78648E-1: CD Digital Signal ProcessorLC78648E, BLOCK DIAGRAM OF IC

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IC1 VHiLC78648E-1: CD Digital Signal Processor(LC78648E) CD-ES900/CD-ES99 LDD LDS FR VVDD PCKIST VVSS PD02 PD01 CONT1 CONT2 CONT3 VSS VDD5 DRF *RES *WRQ DO DI CL CE 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SLCO 1 SLCIST 2 EFMIN 3 RF 4 RFVDD 5 RFVSS 6 FIN1 7 FIN2 8 TIN1 9 TIN2 10 VREF 11 REF1 12 FE 13 TEC 14 TE 15 RFMON 16 JITTC 17 ADAVDD 18 ADAVSS 19 TDO 20 LC78646E 60 DATA 59 BCK 58 LRCK 57 ASDFIN 56 ASDACK 55 ASLRCK 54 16MOUT 53 EFLG 52 C2F 51 XVSS 50 FSX/16MIN 49 XIN 48 XOUT 47 XVDD 46 RVDD 45 RCHO 44 RVSS 43 LVSS 42 LCHO 41 LVDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TEST DOUT VDD (3.3V)VSS MONI5 MONI4 MONI3 MONI2 TEC MONI1 FSEQ V/*P DEFECT SBCK/FG SBCK/CONT6 CONT5 CONT4 GPDAC SLDO SPDO FDO RF TE FE FIN1 FIN2 TIN1 TIN2 REF1 DETECT ADIN ADAVDD ADAVSS JITTC SLCO EFMIN SLCIST PCK PDO1 PDO2 FR PCKIST VVDD VVSS SBCK/FG XIN XOUT 16MOUT XVDD XVSS *RES *WRQ CL CE DI DO VDD5V CONT1, 2, 3 CONT4, 5 SBCK/CONT6 TEST + Ð MIX + Ð+ Ð LPF + Ð TBAL +Ð + Ð TBAL LEVEL SET RAM AGC EQ LPF SW LPF + Ð Ð + PH BH MONI CONT Ð + Ð + RFVDD RFVSS RFMON VREF A/D SERVO PROCESSOR TRACK JUMP AUTO ADJUST APC SLICE LEVEL CONTROL JITTER DETECT SW D/A S/H DRF PLL VCEC CLV,CAV CONTROL CLOCK GENERATOR COMMAND INTERFACE GENERAL-PURPOSE PORTS 8FS DIGITAL FILTER 1bit DAC RUPTURE DEFECT VDD FRAME SYNC DETECT,PROTECT INSERT, EFN DECODE SUBCODE DECODE CRC MONITOR SIGNAL SELECTOR ERROR CORRECTION AUDIO CD INTERPOLATION MUTE ATTENUATION DEEMPHSIS LPF RAM AUDIO OUT SERIAL OUT EXTERNAL AUDIO IN LDD LDS FD0 TD0 SLD0 SPD0 GPDAC DRF FSEQ V/*P VDD VSS MONI1~5 FSK/16MIN C2F EFLG DOUT LRCK BCK DATA ASLRCK ASDQCK ASDFIN LVDD LVSS LCHO RCHO RVDD RVSS Figure 8-3 BLOCK DIAGRAM OF IC 8 - 3

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CD-ES900/CD-ES99
8 – 3
IC1 VHiLC78648E-1: CD Digital Signal Processor(LC78648E)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
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27
28
29
30
31
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33
34
35
36
37
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40
80
79
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41
SLCO
SLCIST
EFMIN
RF
RFVDD
RFVSS
FIN1
FIN2
TIN1
TIN2
VREF
REF1
FE
TEC
TE
RFMON
JITTC
ADAVDD
ADAVSS
TDO
FDO
SPDO
SLDO
GPDAC
CONT4
CONT5
SBCK/CONT6
SBCK/FG
DEFECT
V/*P
FSEQ
MONI1
MONI2
MONI3
MONI4
MONI5
(3.3V)VSS
VDD
DOUT
TEST
LDD
LDS
FR
VVDD
PCKIST
VVSS
PD02
PD01
CONT1
CONT2
CONT3
VSS
VDD5
DRF
*RES
*WRQ
DO
DI
CL
CE
DATA
BCK
LRCK
ASDFIN
ASDACK
ASLRCK
16MOUT
EFLG
C2F
XVSS
FSX/16MIN
XIN
XOUT
XVDD
RVDD
RCHO
RVSS
LVSS
LCHO
LVDD
LC78646E
+
Ð
+
Ð
+
Ð
+
Ð
Ð
Ð
+
+
MIX
LPF
LPF
LPF
TBAL
TBAL
RAM
LEVEL SET
AGC
EQ
SW
PH
BH
+
Ð
+
Ð
+
Ð
+
Ð
MONI
CONT
A/D
SERVO PROCESSOR
TRACK JUMP
AUTO ADJUST
JITTER
DETECT
1bit DAC
8FS
DIGITAL FILTER
GENERAL-PURPOSE
PORTS
COMMAND
INTERFACE
CLOCK
GENERATOR
CLV,CAV
CONTROL
PLL
VCEC
SLICE LEVEL
CONTROL
APC
S/H
D/A
SW
DRF
RUPTURE DEFECT
FRAME SYNC
DETECT,PROTECT INSERT,
EFN DECODE
VDD
SUBCODE DECODE CRC
MONITOR SIGNAL SELECTOR
RAM
ERROR
CORRECTION
AUDIO CD
AUDIO OUT
SERIAL
OUT
EXTERNAL
AUDIO IN
INTERPOLATION
MUTE
ATTENUATION
DEEMPHSIS
LPF
FIN1
FIN2
TIN1
TIN2
REF1
DETECT
ADIN
ADAVDD
ADAVSS
JITTC
SLCO
EFMIN
SLCIST
PCK
PDO1
PDO2
FR
PCKIST
VVDD
VVSS
SBCK/FG
XIN
XOUT
16MOUT
XVDD
XVSS
*RES
*WRQ
CL
CE
DI
DO
VDD5V
CONT1, 2, 3
TEST
CONT4, 5
SBCK/CONT6
LVDD
LVSS
LCHO
RCHO
RVDD
RVSS
ASDFIN
ASDQCK
ASLRCK
DATA
BCK
LRCK
DOUT
EFLG
C2F
FSK/16MIN
MONI1~5
VSS
VDD
V/*P
FSEQ
DRF
GPDAC
SPD0
SLD0
TD0
FD0
LDS
LDD
VREF
RFMON
RFVSS
RFVDD
RF
TEC
TE
FE
Figure 8-3 BLOCK DIAGRAM OF IC