Sharp CD-ES9 Service Manual - Page 85

LC75341

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CD-ES900/CD-ES99 IC601 VHiLC75341/-1: Audio Processor (LC75341) Pin No. 1 2 3 4 5 6 7 8 9-12 13-16 17 18 19 20 21 22 23 24 Terminal Name DI CE VSS LOUT LBASS LTRE LIN LSEL0 L4-1 R1-4 RSEL0 RIN RTRE RBASS ROUT VREF VDD CLK Function Serial data and clock input pin for control. Chip enable pin. Data written into an internal latch in a timing of "H" to "L". Each analog switch is activated. Data transfer enabled at "H" level. Ground pin. Bass band filter comprising capacitor and resistor connection pin and bass/treble output pin. Bass band filter comprising capacitor and resistor connection pin. Treble band filter comprising capacitor and resistor connection pin. Volume + equalizer output pin. Input selector output pin. Input signal pin. Input signal pin. Input selector output pin. Volume + equalizer output pin Treble band filter comprising capacitor and resistor connection pin. Bass band filter comprising capacitor and resistor connection pin. Bass band filter comprising capacitor and resistor connection pin and bass/treble output pin. 0.5x VDD voltage generation block for analog ground. Capacitor of several 10 µF to be connected between VREF and AWSS (VSS) as a countermeasure against power ripple. Supply pin Serial data and clock input pin for control. VSS CE DI CLK VDD VREF 3 2 1 24 23 22 LVref CCB INTERFACE RVref LOUT 4 LBASS 5 LTRE 6 LIN 7 LSEL0 8 CONTROL CIRCUIT CONTROL CIRCUIT CONTROL CIRCUIT 21 ROUT 20 RBASS 19 RTRE 18 RIN 17 RSEL0 DI 1 CE 2 VSS 3 LOUT 4 LBASS 5 LTRE 6 LIN 7 LSEL0 8 L4 9 L3 10 L2 11 L1 12 LC75341 24 CLK 23 VDD 22 VREF 21 ROUT 20 RBASS 19 RTRB 18 RIN 17 RSEL0 16 R4 15 R3 14 R2 13 R1 CD Tuner Tape Video 9 10 11 12 L4 L3 L2 L1 13 14 15 16 R1 R2 R3 R4 Figure 8-5 BLOCK DIAGRAM OF IC 8 - 6

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CD-ES900/CD-ES99
8 – 6
IC601 VHiLC75341/-1: Audio Processor (LC75341)
Pin No.
Terminal Name
Function
1
DI
Serial data and clock input pin for control.
2
CE
Chip enable pin.
Data written into an internal latch in a timing of “H” to “L”.
Each analog switch is activated.
Data transfer enabled at “H” level.
3
VSS
Ground pin.
4
LOUT
Bass band filter comprising
capacitor and resistor connection pin and bass/treble output pin.
5
LBASS
Bass band filter comprising capacitor and resistor connection pin.
6
LTRE
Treble band filter comprising capacitor and resistor connection pin.
7
LIN
Volume + equalizer output pin.
8
LSEL0
Input selector output pin.
9-12
L4-1
Input signal pin.
13-16
R1-4
Input signal pin.
17
RSEL0
Input selector output pin.
18
RIN
Volume + equalizer output pin
19
RTRE
Treble band filter comprising capacitor and resistor connection pin.
20
RBASS
Bass band filter comprising capacitor and resistor connection pin.
21
ROUT
Bass band filter comprising capacitor and resistor connection pin and bass/treble output pin.
22
VREF
0.5x VDD voltage generation
block for analog ground. Capacitor of several 10 µF to be connected between VREF
and AWSS (VSS) as a countermeasure against power ripple.
23
VDD
Supply pin
24
CLK
Serial data and clock input pin for control.
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
LVref
RVref
CONTROL
CIRCUIT
CONTROL
CIRCUIT
CONTROL
CIRCUIT
LOUT
LBASS
LIN
LSEL0
L4
L3
L2
L1
R1
R2
R3
R4
RSEL0
RIN
RTRE
LTRE
RBASS
ROUT
VREF
VDD
CLK
DI
CE
VSS
CCB
INTERFACE
CD
Tuner
Tape
Video
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
LC75341
DI
CE
VSS
LOUT
LBASS
LTRE
LIN
LSEL0
L4
L3
L2
L1
CLK
VDD
VREF
ROUT
RBASS
RTRB
RIN
RSEL0
R4
R3
R2
R1
Figure 8-5 BLOCK DIAGRAM OF IC