Sony DVPNS61 Service Manual - Page 67

Ext. CPU Ready/Busy interrupt signal H: Busy, L: Ready

Page 67 highlights

DVP-NS36/NS37/NS45P/NS55P/NS61P/NS63P Pin No. 100 101 102 Pin name xIFCS IFSDI SCL 103 SDA 104 GPIO 105 IFBSY 106 RXD 107 TXD 108 DVDD3 109 ICE 110 xSYSRST 111 IR 112 INT0 113 DQM0 114 LIMIT SW 115 RD7 116 DVSS 117 RD6 118 RD5 119 DVSS 120 RD4 121 RD3 122 DVDD18 123 RD2 124 RD1 125 RD0 126 RD15 127 DVDD3 128 RD14 129 RD13 130 RD12 131 RD11 132 RD10 133 RD9 134 DVSS 135 RD8 136 RGBSEL (MV-50 only) GPIO (MV-51 only) 137 DQM1 138 RWE# 139 CAS# 140 RAS# 141 DVDD3 142 RCS# 143 BA0 144 DVSS 145 BA1 146 RA10 147 RA0 148 DVSS Type Default High Input PU, SMT Default High-Z Output PU, SMT Default High-Z Output PU, SMT Int PU, SMT Input PU, SMT Default High Output PU, SMT Power Output PU,SMT Input PU,SMT Input SMT Input PU,SMT Output Output Default Low Output Ground Output Output Ground Output Output Power Output Output Output Output Power Output Output Output Output Output Output Ground Output Output Default Low Output Output Output Output Power Output Output Ground Output Output Output Ground Function Chip select for Ext.CPU (Low Active, H/W method) Ext. CPU Serial data Input Hardware IIC clock (use 52.5/105 kHz) Hardware IIC data Not used Ext. CPU Ready/Busy interrupt signal (H: Busy, L: Ready) Hardwared RS232C RXD Hardwared RS232C TXD 3.3V power pin for internal digital circuitry ICE mode enable MT1389 reset input, active Low IR control signal input 8032 external interrupt 0 (for ICE) Mask for DRAM input/output byte 0 Inlimit SW sensor input signal DRAM data bit7 Ground pin for internal digital circuitry DRAM data bit6 DRAM data bit5 Ground pin for internal digital circuitry DRAM data bit4 DRAM data bti3 1.8V power pin for internal digital circuitry DRAM data bit2 DRAM data bit1 DRAM data bit0 DRAM data bit15 3.3V power pin for internal digital circuitry DRAM data bit14 DRAM data bit13 DRAM data bit12 DRAM data bit11 DRAM data bit10 DRAM data bit9 Ground pin for internal circuitry DRAM data bit8 RGB/YCbCr select output signal (H:RGB Disable, L:RGB) Not Used Mask for DRAM input/output byte 1 DRAM write enable DRAM columm address strobe DRAM row address strobe 3.3V power pin for internal digital circuitry DRAM chip select DRAM bank address 0 Ground pin for internal digital circuitry DRAM bank address 1 DRAM address bit10 DRAM address bit0 Ground pin for internal digital circuitry 5-3

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DVP-NS36/NS37/NS45P/NS55P/NS61P/NS63P
5-3
Pin No.
Pin name
Type
Function
100
xIFCS
Default High
Chip select for Ext.CPU (Low Active, H/W method)
101
IFSDI
Input PU, SMT
Ext. CPU Serial data Input
102
SCL
Default High-Z
Hardware IIC clock (use 52.5/105 kHz)
Output PU, SMT
103
SDA
Default High-Z
Hardware IIC data
Output PU, SMT
104
GPIO
Not used
105
IFBSY
Int PU, SMT
Ext. CPU Ready/Busy interrupt signal (H: Busy, L: Ready)
106
RXD
Input PU, SMT
Hardwared RS232C RXD
107
TXD
Default High
Hardwared RS232C TXD
Output PU, SMT
108
DVDD3
Power
3.3V power pin for internal digital circuitry
109
ICE
Output PU,SMT
ICE mode enable
110
xSYSRST
Input PU,SMT
MT1389 reset input, active Low
111
IR
Input SMT
IR control signal input
112
INT0
Input PU,SMT
8032 external interrupt 0 (for ICE)
113
DQM0
Output
Mask for DRAM input/output byte 0
Output Default
114
LIMIT SW
Low
Inlimit SW sensor input signal
115
RD7
Output
DRAM data bit7
116
DVSS
Ground
Ground pin for internal digital circuitry
117
RD6
Output
DRAM data bit6
118
RD5
Output
DRAM data bit5
119
DVSS
Ground
Ground pin for internal digital circuitry
120
RD4
Output
DRAM data bit4
121
RD3
Output
DRAM data bti3
122
DVDD18
Power
1.8V power pin for internal digital circuitry
123
RD2
Output
DRAM data bit2
124
RD1
Output
DRAM data bit1
125
RD0
Output
DRAM data bit0
126
RD15
Output
DRAM data bit15
127
DVDD3
Power
3.3V power pin for internal digital circuitry
128
RD14
Output
DRAM data bit14
129
RD13
Output
DRAM data bit13
130
RD12
Output
DRAM data bit12
131
RD11
Output
DRAM data bit11
132
RD10
Output
DRAM data bit10
133
RD9
Output
DRAM data bit9
134
DVSS
Ground
Ground pin for internal circuitry
135
RD8
Output
DRAM data bit8
Output Default
136
RGBSEL (MV-50 only)
Low
RGB/YCbCr select output signal (H:RGB Disable, L:RGB)
GPIO (MV-51 only)
Not Used
137
DQM1
Output
Mask for DRAM input/output byte 1
138
RWE#
Output
DRAM write enable
139
CAS#
Output
DRAM columm address strobe
140
RAS#
Output
DRAM row address strobe
141
DVDD3
Power
3.3V power pin for internal digital circuitry
142
RCS#
Output
DRAM chip select
143
BA0
Output
DRAM bank address 0
144
DVSS
Ground
Ground pin for internal digital circuitry
145
BA1
Output
DRAM bank address 1
146
RA10
Output
DRAM address bit10
147
RA0
Output
DRAM address bit0
148
DVSS
Ground
Ground pin for internal digital circuitry