Via VB8001-16 User Manual - Page 57

Frequency/Voltage Control

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Chapter 3 Frequency/Voltage Control DRAM Clock The chipset supports synchronous and asynchronous mode between host clock and DRAM clock frequency. Settings: Host CLK, HCLK-33M, HCLK+33M, and By Auto. DRAM Timing By SPD This setting determines whether DRAM timing is configured by reading the contents of the SPD (Serial Presence Detect) EPROM on the DRAM module. Selecting Yes makes SDRAM Cycle Length and Bank Interleave automatically determined by BIOS according to the configurations on the SPD. Settings: Disabled and Enabled. SDRAM Cycle Length Set the time between SDRAM read command and when the data actually becomes available. Bank Interleave Set the interleave mode of the SDRAM interface. Interleaving allows banks of SDRAM to alternate their refresh and access cycles. One bank will undergo its refresh cycle while another is being accessed. This improves performance of the SDRAM by masking the refresh time of each bank. 3-24

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Chapter 3
3-24
Frequency/Voltage Control
DRAM Clock
The chipset supports synchronous and asynchronous mode between host clock
and DRAM clock frequency. Settings:
Host CLK, HCLK-33M, HCLK+33M,
and
By Auto.
DRAM Timing By SPD
This setting determines whether DRAM timing is configured by reading the
contents of the SPD (Serial Presence Detect) EPROM on the DRAM module.
Selecting Yes makes SDRAM Cycle Length and Bank Interleave automatically
determined by BIOS according to the configurations on the SPD. Settings:
Disa-
bled
and
Enabled.
SDRAM Cycle Length
Set the time between SDRAM read command and when the data actually be-
comes available.
Bank Interleave
Set the interleave mode of the SDRAM interface. Interleaving allows banks of
SDRAM to alternate their refresh and access cycles. One bank will undergo its
refresh cycle while another is being accessed. This improves performance of the
SDRAM by masking the refresh time of each bank.