AIWA CDC-X227 Service Manual - Page 31

AIWA CDC-X227 Manual

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Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name HFL SLOF CVCV+ RFSM RFS- SLC SLI D-GND FSC TBC NC DEF CLK CL DAT CE DRF FSS VCC2 REFI VR LF2 PH1 BH1 LDD LDS VCC1 I/O Description The HFL (high frequency level) signal is used to judge whether the main beam is positioned on O the pit or on the mirror. I Sled servo off control input. I CLV error signal input from the DSP. O RF output. O Set the RF gain and the EFM singal's 3T compensation constant together with the RFSM pin. The SLC (slice level control) signal is output to control the DSP's data slice level of the RF O waveform. I Input to control the DSP's data slice level. - Ground of digital signals. O Output for the focus search smoothing capacitor. I The TBC (tracking balance control) signal sets the EF balance variation range. - Not connected. O Disc defect detection output. I Reference clock input. 4.23 MHz is input from the DSP. I Microprocessor command clock input. I Microprocessor command data input. I Microprocessor chip enable input. O DRF (detect RF) is an output to detect the RF level. The FSS (focus search select) signal switches the focus search modes (+/-search / +search with I respect to the reference voltage). (Connected to D-GND) - VCC of servo and digital circuits. - For the connection of bypass capacitor for the reference voltage. O Reference voltage output. - Set the time constant for disc defect detection. - For the connection of a capacitor to hold the RF signal peak. - For the connection of a capacitor to hold the RF signal bottom. O APC circuit output. I APC circuit input. - VCC of RF signal circuits. - 31 -

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Pin No.
Pin Name
I/O
Description
37
HFL
O
The HFL (high frequency level) signal is used to judge whether the main beam is positioned on
the pit or on the mirror.
38
SLOF
I
Sled servo off control input.
39
CV-
I
CLV error signal input from the DSP.
40
CV+
41
RFSM
O
RF output.
42
RFS-
O
Set
the RF gain and the EFM singal's 3T compensation constant together with the RFSM pin.
43
SLC
O
The SLC (slice level control) signal is output to control the DSP's data slice level of the RF
waveform.
44
SLI
I
Input to control the DSP's data slice level.
45
D-GND
-
Ground of digital signals.
46
FSC
O
Output for the focus search smoothing capacitor.
47
TBC
I
The TBC (tracking balance control) signal sets the EF balance variation range.
48
NC
-
Not connected.
49
DEF
O
Disc defect detection output.
50
CLK
I
Reference clock input. 4.23 MHz is input from the DSP.
51
CL
I
Microprocessor command clock input.
52
DAT
I
Microprocessor command data input.
53
CE
I
Microprocessor chip enable input.
54
DRF
O
DRF (detect RF) is an output to detect the RF level.
55
FSS
I
The FSS (focus search select) signal switches the focus search modes (+/-search / +search with
respect to the reference voltage). (Connected to D-GND)
56
VCC2
-
VCC of servo and digital circuits.
57
REFI
-
For the connection of bypass capacitor for the reference voltage.
58
VR
O
Reference voltage output.
59
LF2
-
Set the time constant for disc defect detection.
60
PH1
-
For the connection of a capacitor to hold the RF signal peak.
61
BH1
-
For the connection of a capacitor to hold the RF signal bottom.
62
LDD
O
APC circuit output.
63
LDS
I
APC circuit input.
64
VCC1
-
VCC of RF signal circuits.
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