Dell PowerEdge 6350 Dell PowerEdge Systems 6350 Installation and Troubleshooti - Page 64

parity, address, HP OpenView NNM SE, With Dell OpenManage HIP, User's Guide

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Page 64 highlights

You get a parity error (any error message that contains the word parity) at any time during operation. These errors are usually accompanied by a reference to an address-the location of the portion of memory where the error occurred-which you should record on a copy of the Diagnostics Checklist found in Chapter 12, "Getting Help." You receive the Memory ECC fault detected message from the Dell OpenManage Hardware Instrumentation Package (HIP) server management application. Refer to the Dell OpenManage HIP online help and the HP OpenView NNM SE x.x With Dell OpenManage HIP x.x User's Guide for information about the alert message. The subtests in the System Set Test group check the computer's basic system board components and verify their related functions. The subtests that constitute the System Set Test group and the computer functions they confirm follow: CMOS Confidence Test Checks the NVRAM for accessibility and reliability of data storage by performing a data pattern check and verifying the uniqueness of memory addresses. DMA Controller Test Tests the direct memory access (DMA) controller and verifies the correct operation of its page and channel registers by writing patterns to the registers. Real-Time Clock Test Confirms the functionality and accuracy of the computer's real-time clock (RTC). System Timers Test Checks the timers used by the microprocessor for event counting, frequency generation, and other functions. Only the functions that can be activated by software are tested. Interrupt Controller Test Generates an interrupt on each interrupt request (IRQ) line to verify that devices using that line can communicate with the microprocessor and that the interrupt controllers send the correct memory addresses to the microprocessor. APIC Test Tests that the procedure used to boot a multiprocessor system is able to properly receive interrupts from the input/output (I/O) Advanced Peripheral Interrupt Controller (APIC). 5-14 Dell PowerEdge 6350 Systems Installation and Troubleshooting Guide

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5-14
Dell PowerEdge 6350 Systems Installation and Troubleshooting Guide
²
You get a parity error (any error message that contains the word
parity
) at any
time during operation. These errors are usually accompanied by a reference to an
address
—the location of the portion of memory where the error occurred—which
you should record on a copy of the Diagnostics Checklist found in Chapter 12,
“Getting Help.”
²
You receive the
Memory ECC fault detected
message from the Dell Open-
Manage Hardware Instrumentation Package (HIP) server management application.
Refer to the Dell OpenManage HIP online help and the
HP OpenView NNM SE
x.x
With Dell OpenManage HIP
x.x
User’s Guide
for information about the alert
message
.
6\VWHP±6HW±7HVW±*URXS
The subtests in the System Set Test group check the computer’s basic system board
components and verify their related functions.
6XEWHVWV
The subtests that constitute the System Set Test group and the computer functions
they confirm follow:
²
CMOS Confidence Test
Checks the NVRAM for accessibility and reliability of data storage by performing
a data pattern check and verifying the uniqueness of memory addresses.
²
DMA Controller Test
Tests the direct memory access (DMA) controller and verifies the correct opera-
tion of its page and channel registers by writing patterns to the registers.
²
Real-Time Clock Test
Confirms the functionality and accuracy of the computer’s real-time clock (RTC).
²
System Timers Test
Checks the timers used by the microprocessor for event counting, frequency
generation, and other functions. Only the functions that can be activated by soft-
ware are tested.
²
Interrupt Controller Test
Generates an interrupt on each interrupt request (IRQ) line to verify that devices
using that line can communicate with the microprocessor and that the interrupt
controllers send the correct memory addresses to the microprocessor.
²
APIC Test
Tests that the procedure used to boot a multiprocessor system is able to properly
receive interrupts from the input/output (I/O) Advanced Peripheral Interrupt
Controller (APIC).