Foxconn Cinema Deluxe English Manual. - Page 44

► HT Uplink Width / HT DownLink Width

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3 This option helps lowering down the CPU frequency and voltage when system is idling. When the CPU speed is slowing down, the temperature will drop as well. ► CPU Voltage Offset This option is used to change the CPU voltage in a step of 25mV. The voltage can be incremented from +25mV to +775mV. ► Reference Clock (FSB) This clock signal is multiplied to create CPU Core, CPU Uncore, Memory and HyperTransport Frequencies. ► PCIEx16 Slot Clock This option is used to adjust the speed of PCI Express slot. It may enhance the graphics card speed. ► CPU-NB HT Multiplier HT stands for HyperTransport bus. The CPUNB HT Multiplier option controls the physical speed of the CPU to Northbridge HT link using multipliers ranging 1x to 13x. The physical speed of the link is determined by multiplying the CPU FSB with the CPUNB HT Speed setting. ► HT Uplink Width / HT DownLink Width The coherency refers to the caching of memory, and the HT links between processors are coherent HT links as the HT protocol includes messages for managing the cache protocol. Other (non processor-processor) HT links are Non-Coherent HT links, as they do not have memory cache. The HyperTransport link width and frequency are initialized between the adjacent coherent and/or noncoherent HyperTransport technology devices during the reset sequence. It is highly recommended to set to [Auto] for overall performance. ► Advanced HT Setting This option is used to configure HyperTransport Function. ► NB VID This option is used to specify the alternate VID while in low power states. ► NB Voltage Offset This option is used to change the North Bridge voltage in a step of 30mV. The voltage can be incremented from +30mV to +360mV. ► HT/SB Voltage Offset This option is used to change the HyperTransport/South Bridge voltage in a step of 30mV. The voltage can be incremented from +30mV to +360mV. ► DRAM Voltage Offset This option is used to change the DRAM voltage in a step of 50mV. The voltage can be incremented from +50mV to +600mV. 37

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3
37
This option helps lowering down the CPU frequency and voltage when system is idling. When
the CPU speed is slowing down, the temperature will drop as well.
► CPU Voltage Offset
This option is used to change the CPU voltage in a step of 25mV. The voltage can be incre
-
mented from +25mV to +775mV.
► Reference Clock (FSB)
This clock signal is multiplied to create CPU Core, CPU Uncore, Memory and HyperTransport
Frequencies.
► PCIEx16 Slot Clock
This option is used to adjust the speed of PCI Express slot. It may enhance the graphics card
speed.
► CPU-NB HT Multiplier
HT stands for HyperTransport bus. The CPU<->NB HT Multiplier option controls the physical
speed of the CPU to Northbridge HT link using multipliers ranging 1x to 13x. The physical
speed of the link is determined by multiplying the CPU FSB with the CPU<->NB HT Speed
setting.
► HT Uplink Width / HT DownLink Width
The coherency refers to the caching of memory, and the HT links between processors are co-
herent HT links as the HT protocol includes messages for managing the cache protocol. Other
(non processor-processor) HT links are Non-Coherent HT links, as they do not have memory
cache.
The HyperTransport link width and frequency are initialized between the adjacent coherent
and/or noncoherent HyperTransport technology devices during the reset sequence.
It is highly recommended to set to [Auto] for overall performance.
► Advanced HT Setting
This option is used to configure HyperTransport Function.
► NB VID
This option is used to specify the alternate VID while in low power states.
► NB Voltage Offset
This option is used to change the North Bridge voltage in a step of 30mV. The voltage can be
incremented from +30mV to +360mV.
► HT/SB Voltage Offset
This option is used to change the HyperTransport/South Bridge voltage in a step of 30mV. The
voltage can be incremented from +30mV to +360mV.
► DRAM Voltage Offset
This option is used to change the DRAM voltage in a step of 50mV. The voltage can be incre
-
mented from +50mV to +600mV.