Foxconn Cinema Deluxe English Manual. - Page 48

Memory Features

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3 ► tRC (Active-to-Active/Auto-Refresh Command Period) This item allows you to set the row cycle time (in clock cycles). tRC = tRAS + tRP. ► tWR (Write Recovery) This item allows you to select the write recovery time (in clock cycles). ► tRRD (Active-to-Active of a Different Bank) This item allows you to select a delay time (in clock cycles) between the RAS# and RAS# strobe signals. ► tRWTTO (Read-to-Write Turnaround for Data. Optional only if CPU supports) This timing parameter ensures read-to-write data-bus turnaround. ► tWRRD (Write to Read DIMM Termination Turn-around. Optional only if CPU supports) This timing parameter accounts for termination timing when a write is followed by a read to a different DIMM. ► tWTR (Internal Write to Read Command Delay) This item allows you to select a delay time (in clock cycles) between sending the last data from a write operation to the memory and issuing a read command. ► tWRWR (Write to Write Timing. Optional only if CPU supports) This timing parameter accounts for turn-around timing when a write is followed by a write to a different DIMM. ► tRDRD (Read to Read Timing. Optional only if CPU supports) This timing parameter accounts for turn-around and termination timing when a read is followed by a read to a different chip select. ► tRFC0, 1, 2, 3 (Auto-Refresh-to-Active/Auto-Refresh Command Period) Refresh to Refresh or Refresh to Active command interval. Trfc3: auto-refresh row cycle time for logical DIMM 3 Trfc2: auto-refresh row cycle time for logical DIMM 2 Trfc1: auto-refresh row cycle time for logical DIMM 1 Trfc0: auto-refresh row cycle time for logical DIMM 0 Memory Features CMOS Setup Utility - Copyright (C) 1985-2009, American Megatrends, Inc. Memory Features Memory Features Help Item Bank Inter Leaving [Auto] Sligthly improves Channel Inter leaving [XOR of Address bit] memory performance Enable Clock to All DIMMs [Disabled] MemCLK Tristate C3/ATLVID [Disabled] Memory Hole Remapping [Enabled] DCT Unganged Mode [Always] Power Down Enable [Enabled] Power Down Mode [Channel] Auto Tweak Performance [Disabled] DRAM Config_High Control [Auto] Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help F2/F3:Change Colors F9:Optimized Defaults 41

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► tRC (Active-to-Active/Auto-Refresh Command Period)
This item allows you to set the row cycle time (in clock cycles). tRC = tRAS + tRP.
► tWR (Write Recovery)
This item allows you to select the write recovery time (in clock cycles).
► tRRD (Active-to-Active of a Different Bank)
This item allows you to select a delay time (in clock cycles) between the RAS# and RAS#
strobe signals.
► tRWTTO (Read-to-Write Turnaround for Data. Optional only if CPU supports)
This timing parameter ensures read-to-write data-bus turnaround.
► tWRRD (Write to Read DIMM Termination Turn-around. Optional only if CPU supports)
This timing parameter accounts for termination timing when a write is followed by a read to a
different DIMM.
► tWTR (Internal Write to Read Command Delay)
This item allows you to select a delay time (in clock cycles) between sending the last data from
a write operation to the memory and issuing a read command.
► tWRWR (Write to Write Timing. Optional only if CPU supports)
This timing parameter accounts for turn-around timing when a write is followed by a write to a
different DIMM.
► tRDRD (Read to Read Timing. Optional only if CPU supports)
This timing parameter accounts for turn-around and termination timing when a read is followed
by a read to a different chip select.
► tRFC0, 1, 2, 3 (Auto-Refresh-to-Active/Auto-Refresh Command Period)
Refresh to Refresh or Refresh to Active command interval.
Trfc3: auto-refresh row cycle time for logical DIMM 3
Trfc2: auto-refresh row cycle time for logical DIMM 2
Trfc1: auto-refresh row cycle time for logical DIMM 1
Trfc0: auto-refresh row cycle time for logical DIMM 0
Memory Features
CMOS Setup Utility - Copyright (C) 1985-2009, American Megatrends, Inc.
Memory Features
Memory Features
Help Item
Bank Inter Leaving
Sligthly improves
Channel Inter leaving
[XOR of Address bit]
memory performance
Enable Clock to All DIMMs
[Disabled]
MemCLK Tristate C3/ATLVID
[Disabled]
Memory Hole Remapping
[Enabled]
DCT Unganged Mode
[Always]
Power Down Enable
[Enabled]
Power Down Mode
[Channel]
Auto Tweak Performance
[Disabled]
DRAM Config_High Control
[Auto]
↑↓←→:Move
Enter:Select
+/-/:Value
F10:Save
ESC:Exit
F1:General Help
F2/F3:Change Colors
F9:Optimized Defaults
[Auto]