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Fujitsu MJA2500BH Maintenance Manual - Page 104

Command descriptions, READ SECTOR S

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Interface 5.3.2 Command descriptions The contents of the shadow block registers to be necessary for issuing a command and the example indication of the shadow block registers at command completion are shown as following in this subsection. Example: READ SECTOR (S) At command issuance (Shadow Block Registers setting contents) Bit 7 6 5 4 3210 CM 0 0 1 0 0000 DH x L x x HD No./LBA CH EXP LBA (47-40) CH Start cylinder address [MSB] / LBA (23-16) CL EXP LBA (39-32) CL Start cylinder address [LSB] / LBA (15-8) SN EXP LBA (31-24) SN Start sector No. / LBA (7-0) SC EXP Transfer sector count (15-8) SC Transfer sector count (7-0) FR EXP xx FR xx At command completion (Shadow Block Registers to be read) Bit 7 6 5 4 321 0 ST Status information DH x L x x HD No./LBA CH EXP LBA (47-40) CH End cylinder address [MSB] / LBA (23-16) CL EXP LBA (39-32) CL End cylinder address [LSB] / LBA (15-8) SN EXP LBA (31-24) SN End sector No. / LBA (7-0) SC EXP X '00' SC X '00' ER Error information CH (EXP): CL (EXP): CM: DH: ER: FR (EXP): L: SN (EXP): SC (EXP): ST: x, xx: Note: 1. 2. 3. Cylinder High Field (EXP) Cylinder Low Field (EXP) Command Field Device/Head Field Error Field Features Field (EXP) LBA (Logical Block Address) setting bit Sector Number Field (EXP) Sector Count Field (EXP) Status Field Don't care (setting is not necessary). When the L bit is specified to 1, the lower 4 bits of the DH field and all bits of the CH field, CL and SN fields indicate the LBA bits (bits of the DH filed are the MSB (most significant bit) and bits of the SN field are the LSB (least significant bit). At error occurrence, the SC field indicates the remaining sector count of data transfer. Bit indication is omitted in each command description. 5-30 C141-E293

Section	Page
Front Cover	1
FOR SAFE OPERATION	2
Revision History	3
Preface	5
Important Alert Items	9
Manual Organization	11
Contents	13
Illustrations	19
Figures	19
Tables	21
CHAPTER 1 Device Overview	23
1.1 Features	24
1.1.1 Functions and performance	24
1.1.2 Adaptability	24
1.1.3 Interface	25
1.2 Device Specifications	27
1.2.1 Specifications summary	27
1.2.2 Model and product number	28
1.3 Power Requirements	29
1.4 Environmental Specifications	32
1.5 Acoustic Noise	33
1.6 Shock and Vibration	33
1.7 Reliability	34
1.8 Error Rate	35
1.9 Media Defects	35
1.10 Load/Unload Function	35
1.10.1 Recommended power-off sequence	36
1.11 Advanced Power Management (APM)	36
1.12 Interface Power Management (IPM)	38
1.12.1 Host-initiated interface power management (HIPM)	38
1.12.2 Device-initiated interface power management (DIPM)	38
CHAPTER 2 Device Configuration	41
2.1 Device Configuration	42
2.2 System Configuration	43
2.2.1 SATA interface	43
2.2.2 Drive connection	43
CHAPTER 3 Installation Conditions	45
3.1 Dimensions	46
3.2 Mounting	47
3.3 Connections with Host System	53
3.3.1 Device connector	53
3.3.2 Signal segment and power supply segment	54
3.3.3 Connector specifications for host system	54
3.3.4 SATA interface cable connection	55
3.3.5 Note about SATA interface cable connection	55
CHAPTER 4 Theory of Device Operation	57
4.1 Outline	58
4.2 Subassemblies	58
4.2.1 Disk	58
4.2.2 Spindle	58
4.2.3 Actuator	58
4.2.4 Air filter	59
4.3 Circuit Configuration	59
4.4 Power-on Sequence	62
4.5 Self-calibration	64
4.5.1 Self-calibration contents	64
4.5.2 Execution timing of self-calibration	65
4.5.3 Command processing during self-calibration	65
4.6 Read/write Circuit	66
4.6.1 Read/write preamplifier (PreAMP)	66
4.6.2 Write circuit	66
4.6.3 Read circuit	67
4.6.4 Digital PLL circuit	67
4.7 Servo Control	68
4.7.1 Servo control circuit	68
4.7.2 Data-surface servo format	70
4.7.3 Servo frame format	72
4.7.4 Actuator motor control	73
4.7.5 Spindle motor control	74
CHAPTER 5 Interface	75
5.1 Physical Interface	76
5.1.1 Interface signals	76
5.1.2 Signal interface regulation	78
5.1.3 Electrical specifications	80
5.1.4 Connector pinouts	81
5.1.5 P11 function	82
5.1.6 Hot Plug	84
5.2 Logical Interface	85
5.2.1 Communication layers	86
5.2.2 Outline of the Shadow Block Register	87
5.2.3 Outline of the frame information structure (FIS)	88
5.2.4 Shadow block registers	96
5.3 Host Commands	101
5.3.1 Command code and parameters	101
5.3.2 Command descriptions	104
5.3.3 Error posting	247
5.4 Command Protocol	249
5.4.1 Non-data command protocol	250
5.4.2 PIO data-in command protocol	252
5.4.3 PIO data-out command protocol	254
5.4.4 DMA data-in command protocol	256
5.4.5 DMA data-out command protocol	257
5.4.6 Native Command Queuing protocol	258
5.5 Power-on and COMRESET	261
CHAPTER 6 Operations	263
6.1 Reset and Diagnosis	264
6.1.1 Response to power-on	264
6.1.2 Response to COMRESET	266
6.1.3 Response to a software reset	269
6.2 Power Save	270
6.2.1 Power save mode	270
6.2.2 Power commands	272
6.3 Power Save Controlled by Interface Power Management (IPM)	273
6.3.1 Power save mode of the interface	273
6.4 Read-ahead Cache	275
6.4.1 Data buffer structure	275
6.4.2 Caching operation	276
6.4.3 Using the read segment buffer	278
6.5 Write Cache	282
6.5.1 Cache operation	282
CHAPTER 7 Maintenance and Diagnosis	285
7.1 Maintenance	286
7.1.1 Rules for maintenance	286
7.1.2 Maintenance requirements	287
7.1.3 Maintenance levels	289
7.1.4 Disk drive revision number	290
7.1.5 Tools and test equipment	292
7.1.6 Self-diagnostics	292
7.1.7 Test	292
7.2 Operation Confirmation	295
7.2.1 Operation test	295
7.2.2 Diagnostic test	295
7.3 Troubleshooting Procedure	296
7.3.1 Troubleshooting procedure	296
7.3.2 Troubleshooting disk drive replaced in field	296
7.3.3 Troubleshooting at factory	298
7.4 Disk Drive Removal Procedure	299
7.5 Spare Disk Drive	299
Glossary	301
Acronyms and Abbreviations	305
Index	307
Comment Form	315