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Fujitsu MJA2500BH Maintenance Manual - Page 95

Set Device Bits - Device to Host, Set Device Bits FIS

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5.2.3.9 Set Device Bits - Device to Host 5.2 Logical Interface Error R Status Hi R Status Lo R I R Reserved (0) FIS Type (A1h) 0 SActive 31:0 1 Figure 5.11 Set Device Bits FIS The Set Device Bits Device to Host FIS is used by the device to load Shadow Command Block bits for which the device has exclusive write access. These bits are the eight bits of the Error register and six of the eight bits of the Status register. This FIS does not alter bit 7, BSY, or bit 3, DRQ, of the Shadow Status register. FIS Type - Set to a value of A1h. Defines the rest of the FIS fields. Defines the length of the FIS as two Dwords. I - Interrupt Bit. This bit signals the host adapter to enter an interrupt pending state if both the BSY bit and the DRQ bit in the shadow Status register are zero when the frame is received. Error - Contains the new value of the Error register of the Shadow Register Block. Status-Hi - Contains the new value of bits 6, 5, and 4 of the Status register of the Shadow Register Block. Status-Lo - Contains the new value of bits 2,1, and 0 of the Status register of the Shadow Register Block. SActive - The SActive field of the Set Device Bits FIS communicates successful completion notification for each of up to 32 queued commands. The field is bit-significant and the device sets bit positions to one for each command tag it is indicating successful completion notification for. The device may set more than one bit to one if it is explicitly aggregating successful status returns. The device shall only indicate completion notification for a command if it has completed successfully. C141-E293 5-21

Section	Page
Front Cover	1
FOR SAFE OPERATION	2
Revision History	3
Preface	5
Important Alert Items	9
Manual Organization	11
Contents	13
Illustrations	19
Figures	19
Tables	21
CHAPTER 1 Device Overview	23
1.1 Features	24
1.1.1 Functions and performance	24
1.1.2 Adaptability	24
1.1.3 Interface	25
1.2 Device Specifications	27
1.2.1 Specifications summary	27
1.2.2 Model and product number	28
1.3 Power Requirements	29
1.4 Environmental Specifications	32
1.5 Acoustic Noise	33
1.6 Shock and Vibration	33
1.7 Reliability	34
1.8 Error Rate	35
1.9 Media Defects	35
1.10 Load/Unload Function	35
1.10.1 Recommended power-off sequence	36
1.11 Advanced Power Management (APM)	36
1.12 Interface Power Management (IPM)	38
1.12.1 Host-initiated interface power management (HIPM)	38
1.12.2 Device-initiated interface power management (DIPM)	38
CHAPTER 2 Device Configuration	41
2.1 Device Configuration	42
2.2 System Configuration	43
2.2.1 SATA interface	43
2.2.2 Drive connection	43
CHAPTER 3 Installation Conditions	45
3.1 Dimensions	46
3.2 Mounting	47
3.3 Connections with Host System	53
3.3.1 Device connector	53
3.3.2 Signal segment and power supply segment	54
3.3.3 Connector specifications for host system	54
3.3.4 SATA interface cable connection	55
3.3.5 Note about SATA interface cable connection	55
CHAPTER 4 Theory of Device Operation	57
4.1 Outline	58
4.2 Subassemblies	58
4.2.1 Disk	58
4.2.2 Spindle	58
4.2.3 Actuator	58
4.2.4 Air filter	59
4.3 Circuit Configuration	59
4.4 Power-on Sequence	62
4.5 Self-calibration	64
4.5.1 Self-calibration contents	64
4.5.2 Execution timing of self-calibration	65
4.5.3 Command processing during self-calibration	65
4.6 Read/write Circuit	66
4.6.1 Read/write preamplifier (PreAMP)	66
4.6.2 Write circuit	66
4.6.3 Read circuit	67
4.6.4 Digital PLL circuit	67
4.7 Servo Control	68
4.7.1 Servo control circuit	68
4.7.2 Data-surface servo format	70
4.7.3 Servo frame format	72
4.7.4 Actuator motor control	73
4.7.5 Spindle motor control	74
CHAPTER 5 Interface	75
5.1 Physical Interface	76
5.1.1 Interface signals	76
5.1.2 Signal interface regulation	78
5.1.3 Electrical specifications	80
5.1.4 Connector pinouts	81
5.1.5 P11 function	82
5.1.6 Hot Plug	84
5.2 Logical Interface	85
5.2.1 Communication layers	86
5.2.2 Outline of the Shadow Block Register	87
5.2.3 Outline of the frame information structure (FIS)	88
5.2.4 Shadow block registers	96
5.3 Host Commands	101
5.3.1 Command code and parameters	101
5.3.2 Command descriptions	104
5.3.3 Error posting	247
5.4 Command Protocol	249
5.4.1 Non-data command protocol	250
5.4.2 PIO data-in command protocol	252
5.4.3 PIO data-out command protocol	254
5.4.4 DMA data-in command protocol	256
5.4.5 DMA data-out command protocol	257
5.4.6 Native Command Queuing protocol	258
5.5 Power-on and COMRESET	261
CHAPTER 6 Operations	263
6.1 Reset and Diagnosis	264
6.1.1 Response to power-on	264
6.1.2 Response to COMRESET	266
6.1.3 Response to a software reset	269
6.2 Power Save	270
6.2.1 Power save mode	270
6.2.2 Power commands	272
6.3 Power Save Controlled by Interface Power Management (IPM)	273
6.3.1 Power save mode of the interface	273
6.4 Read-ahead Cache	275
6.4.1 Data buffer structure	275
6.4.2 Caching operation	276
6.4.3 Using the read segment buffer	278
6.5 Write Cache	282
6.5.1 Cache operation	282
CHAPTER 7 Maintenance and Diagnosis	285
7.1 Maintenance	286
7.1.1 Rules for maintenance	286
7.1.2 Maintenance requirements	287
7.1.3 Maintenance levels	289
7.1.4 Disk drive revision number	290
7.1.5 Tools and test equipment	292
7.1.6 Self-diagnostics	292
7.1.7 Test	292
7.2 Operation Confirmation	295
7.2.1 Operation test	295
7.2.2 Diagnostic test	295
7.3 Troubleshooting Procedure	296
7.3.1 Troubleshooting procedure	296
7.3.2 Troubleshooting disk drive replaced in field	296
7.3.3 Troubleshooting at factory	298
7.4 Disk Drive Removal Procedure	299
7.5 Spare Disk Drive	299
Glossary	301
Acronyms and Abbreviations	305
Index	307
Comment Form	315