Gigabyte GA-6PXSVL Manual - Page 47

CPU Power Management Configuration

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2-2-3-1 CPU Power Management Configuration CPU Power Management Configuration Power Technology Configure the power management features. Options available: Disable/Energy Efficient/Custom. Default setting is Custom. EIST (Enhanced Intel SpeedStep Technology) Conventional Intel SpeedStep Technology switches both voltage and frequency in tandem between high and low levels in response to processor load. Options available: Enabled/Disabled. Default setting is Enabled. Turbo Mode When this item is enabled, tje processor will automatically ramp up the clock speed of 1-2 of its processing cores to improve its performance. When this item is disabled, the processor will not overclock any of its core. Options available: Enabled/Disabled. Default setting is Enabled. P-STATE Coordination In HW_ALL mode, the processor hardware is responsible for coordinating the P-state among logical processors dependencies. The OS is responsible for keeping the P-state request up to date on all logical processors. In SW_ALL mode, the OS Power Manager is responsible for coordinating the P-state among logical processors with dependencies and must initiate the transition on all of those Logical Processors. In SW_ANY mode, the OS Power Manager is responsible for coordinating the P-state among logical processors with dependencies and may initiate the transition on any of those Logical Processors. - 47 - BIOS Setup

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- 47 -
BIOS Setup
2-2-3-1 CPU Power Management Configuration
CPU Power Management Configuration
Power Technology
Configure the power management features.
Options available: Disable/Energy Efficient/Custom. Default setting is
Custom
.
EIST (Enhanced Intel SpeedStep Technology)
Conventional Intel SpeedStep Technology switches both voltage and frequency in tandem between high
and low levels in response to processor load.
Options available: Enabled/Disabled. Default setting is
Enabled
.
Turbo Mode
When this item is enabled, tje processor
will automatically
ramp up the clock speed of 1-2 of its
processing cores to improve its performance.
When this item is disabled, the processor will not overclock any of its core.
Options available: Enabled/Disabled. Default setting is
Enabled
.
P-STATE Coordination
In HW_ALL mode, the processor hardware is responsible for coordinating the P-state among logical
processors dependencies. The OS is responsible for keeping the P-state request up to date on all
logical processors.
In SW_ALL mode, the OS Power Manager is responsible for coordinating the P-state among logical
processors with dependencies and must initiate the transition on all of those Logical Processors.
In SW_ANY mode, the OS Power Manager is responsible for coordinating the P-state among logical
processors with dependencies and may initiate the transition on any of those Logical Processors.