Hitachi 7K100 Hard Drive Specifications - Page 51
Signal descriptions
UPC - 683728198671
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Table 25: Special signal definitions for Ultra DMA Special Definition (for Ultra DMA) Conventional Definition Write Operation Read Operation DDMARDYHSTROBE STOP HDMARDYDSTROBE STOP IORDY DIORDIOWDIORIORDY DIOW- 7.4 Signal descriptions DD00-DD15 A 16-bit bi-directional data bus between the host and the drive. The lower 8 lines, DD00-07, are used for Register and ECC access. All 16 lines, DD00-15, are used for data transfer. These are 3-state lines with 16mA current sink capability. DA00-DA02 These are addresses used to select the individual register in the drive. CS0The chip select signal generated from the Host address bus. When active, one of the Command Block Registers [Data, Error (Features when written), Sector Count, Sector Number, Cylinder Low, Cylinder High, Drive/Head and Status (Command when written) register] can be selected. CS1The chip select signal generated from the Host address bus. When active, one of the Control Block Registers [Alternate Status (Device Control when written) and Drive Address register] can be selected. RESETThis line is used to reset the drive. It shall be kept at a Low logic state during power up and kept High thereafter. DIOWThe rising edge of this signal holds data from the data bus to a register or data register of the drive. DIORWhen this signal is low, it enables data from a register or data register of the drive onto the data bus. The data on the bus shall be latched on the rising edge of DIOR- INTRQ The interrupt is enabled only when the drive is selected and the host activates the IEN- bit in the Device Control Register. Otherwise, this signal is in high impedance state regardless of the state of the IRQ bit. The interrupt is set when the IRQ bit is set by the drive CPU. The IRQ is reset to zero by a host read of the status register or a write to the Command Register. This signal is a 3-state line with 16mA of sink capability. Travelstar 7K100 Hard Disk Drive Specification 37