Hitachi 7K100 Hard Drive Specifications - Page 74
Alternate Status Register, Command Register, Data Register
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10.1 Alternate Status Register Table 39: Alternate Status Register 7 6 5 4 3 2 1 0 BSY RDY DF DSC DRQ COR IDX ERR This register contains the same information as the Status Register. The only difference between this register and the Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a pending interrupt. See Section 10.13 "Status Register," on page 64 for the definition of the bits in this register. 10.2 Command Register This register contains the command code being sent to the device. Command execution begins immediately after this register is written. The command set is shown in Table 53: "Command Set (1 of 2)," on page 93 and Table 54: "Command Set (2 of 2)," on page 94. All other registers required for the command must be set up before writing to the Command Register. 10.3 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command and the configuration information is transferred on an Identify Device command. All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO only. The register contains valid data only when DRQ = 1 is in the Status Register. Travelstar 7K100 Hard Disk Drive Specification 60