IBM DARA-206000 Hard Drive Specifications - Page 78

Command Register, Cylinder High Register, Cylinder Low Register, Data Register

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Alternate Status Register 7 6 5 BSY RDY DF 4 3 2 1 0 DSC DRQ COR IDX ERR Figure 51. Alternate Status Register This register contains the same information as the Status Register. The only difference is that reading this register does not imply interrupt acknowledge or clear a pending interrupt. See 9.13, "Status Register" on page 71 for the definition of the bits in this register. 9.2 Command Register This register contains the command code being sent to the device. Command execution begins immediately after this register is written. The command set is shown in Figure 68 on page 103. All other registers required for the command must be set up before writing the Command Register. 9.3 Cylinder High Register This register contains the high order bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number. In LBA Mode this register contains Bits 16-23. At the end of the command, this register is updated to reflect the current LBA Bits 16-23. The cylinder number may be from zero to the number of cylinders minus one. 9.4 Cylinder Low Register This register contains the low order 8 bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number. In LBA Mode this register contains Bits 8-15. At the end of the command, this register is updated to reflect the current LBA Bits 8-15. The cylinder number may be from zero to the number of cylinders minus one. 9.5 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command, and configuration information is transferred on an Identify Device command. All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO only. The register contains valid data only when D R Q = 1 in the Status Register. 68 OEM Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1

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Alternate Status Register
7
6
5
4
3
2
1
0
BSY
RDY
DF
DSC
DRQ
COR
IDX
ERR
Figure 51. Alternate Status Register
This register contains the same information as the Status Register.
The only difference is that reading this
register does not imply interrupt acknowledge or clear a pending interrupt.
See 9.13, “Status Register” on
page 71 for the definition of the bits in this register.
9.2
Command Register
This register contains the command code being sent to the device. Command execution begins immediately
after this register is written.
The command set is shown in Figure 68 on page 103.
All other registers required for the command must be set up before writing the Command Register.
9.3
Cylinder High Register
This register contains the high order bits of the starting cylinder address for any disk access.
At the end of
the command, this register is updated to reflect the current cylinder number.
In LBA Mode this register contains Bits 16-23. At the end of the command, this register is updated to reflect
the current LBA Bits 16-23.
The cylinder number may be from zero to the number of cylinders minus one.
9.4
Cylinder Low Register
This register contains the low order 8 bits of the starting cylinder address for any disk access.
At the end of
the command, this register is updated to reflect the current cylinder number.
In LBA Mode this register contains Bits 8-15. At the end of the command, this register is updated to reflect
the current LBA Bits 8-15.
The cylinder number may be from zero to the number of cylinders minus one.
9.5
Data Register
This register is used to transfer data blocks between the device data buffer and the host.
It is also the register
through which sector information is transferred on a Format Track command, and configuration information
is transferred on an Identify Device command.
All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide.
Data transfers are
PIO only.
The register contains valid data only when DRQ=1 in the Status Register.
68
OEM Specifications of DARA-2xxxxx 2.5 inch HDD Rev 2.1