Intel BLKDG43NB Product Specification - Page 73

Error Messages and Beep Codes Table 41. Port 80h POST Codes POST Code Description of POST Operation Host Processor 10 Power-on initialization of the host processor (Boot Strap Processor) 11 Host processor Cache initialization (including APs) 12 Starting Application processor initialization 13 SMM initialization Chipset 21 Initializing a chipset component Memory 22 Reading SPD from memory DIMMs 23 Detecting presence of memory DIMMs 24 Programming timing parameters in the memory controller and the DIMMs 25 Configuring memory 26 Optimizing memory settings 27 Initializing memory, such as ECC init 28 Testing memory PCI Bus 50 Enumerating PCI busses 51 Allocating resources to PCI bus 52 53 - 57 Hot Plug PCI controller initialization Reserved for PCI Bus USB 58 Resetting USB bus 59 Reserved for USB ATA/ATAPI/SATA 5A Resetting PATA/SATA bus and all devices 5B Reserved for ATA SMBus 5C Resetting SMBus 5D Reserved for SMBus Local Console 70 Resetting the VGA controller 71 Disabling the VGA controller 72 Enabling the VGA controller Remote Console 78 Resetting the console controller 79 Disabling the console controller 7A Enabling the console controller continued 73