Intel D2550DC2 Technical product specification - Page 72

Table 36., Port 80h POST Codes, Intel Desktop Board D2550DC2 Technical Product Specification

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Intel Desktop Board D2550DC2 Technical Product Specification Table 36. Port 80h POST Codes Port 80 Code Progress Code Enumeration ACPI S States 0x00,0x01,0x02,0x03,0x04,0x05 Entering S0, S2, S3, S4, or S5 state 0x10,0x20,0x30 Resuming from S2, S3, S4, or S5 state 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x21 0x24 0x25 0x27 0x28 0x31 0x33 0x34 0x41 0x42 0x43 0x44 0x45 0x46 PEI before MRC PEI Platform driver Set boot mode, GPIO init Early chipset register programming Basic chipset initialization LAN init Exit early platform init driver PEI SMBUS SMBUS driver init Entry to SMBUS execute read/write Exit SMBUS execute read/write Memory MRC entry point Detecting presence of memory DIMMs Override Detected DIMM settings Configuring memory. Testing memory PEIMs/Recovery Crisis Recovery has initiated Loading recovery capsule Start recovery capsule / valid capsule is found CPU Initialization CPU PEI Phase Begin CPU PEI Init XMM instruction enabling End CPU PEI Init CPU PEI SMM Phase Begin CPU SMM Init smm relocate bases Smm relocate bases for APs End CPU SMM Init continued 72

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Intel Desktop Board D2550DC2 Technical Product Specification
72
Table 36.
Port 80h POST Codes
Port 80 Code
Progress Code Enumeration
ACPI S States
0x00,0x01,0x02,0x03,0x04,0x05
Entering S0, S2, S3, S4, or S5 state
0x10,0x20,0x30
Resuming from S2, S3, S4, or S5 state
PEI before MRC
PEI Platform driver
0x11
Set boot mode, GPIO init
0x12
Early chipset register programming
0x13
Basic chipset initialization
0x14
LAN init
0x15
Exit early platform init driver
PEI SMBUS
0x16
SMBUS driver init
0x17
Entry to SMBUS execute read/write
0x18
Exit SMBUS execute read/write
Memory
0x21
MRC entry point
0x24
Detecting presence of memory DIMMs
0x25
Override Detected DIMM settings
0x27
Configuring memory.
0x28
Testing memory
PEIMs/Recovery
0x31
Crisis Recovery has initiated
0x33
Loading recovery capsule
0x34
Start recovery capsule / valid capsule is found
CPU Initialization
CPU PEI Phase
0x41
Begin CPU PEI Init
0x42
XMM instruction enabling
0x43
End CPU PEI Init
CPU PEI SMM Phase
0x44
Begin CPU SMM Init smm relocate bases
0x45
Smm relocate bases for APs
0x46
End CPU SMM Init
continued