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Intel D2550DC2 Technical product specification - Page 73

Board Status and Error Messages, Port 80 Code, Progress Code Enumeration, CPU DXE Phase, I/O BUSES

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Board Status and Error Messages Table 36. Port 80h POST Codes (continued) Port 80 Code Progress Code Enumeration CPU DXE Phase 0x47 0x48 0x49 CPU DXE Phase begin Refresh memory space attributes according to MTRRs Load the microcode if needed 0x4A Initialize strings to HII database 0x4B Initialize MP support 0x4C CPU DXE Phase End CPU DXE SMM Phase 0x4D CPU DXE SMM Phase begin 0x4E 0x4F 0x50 Relocate SM bases for all APs CPU DXE SMM Phase end I/O BUSES Enumerating PCI buses 0x51 Allocating resources to PCI bus 0x52 Hot Plug PCI controller initialization USB 0x58 Resetting USB bus 0x59 Reserved for USB 0x5A 0x5B ATA/ATAPI/SATA Resetting PATA/SATA bus and all devices Reserved for ATA BDS 0x60 BDS driver entry point initialize 0x61 BDS service routine entry point (can be called multiple times) 0x62 BDS Step2 0x63 BDS Step3 0x64 0x65 0x66 BDS Step4 BDS Step5 BDS Step6 0x67 BDS Step7 0x68 BDS Step8 0x69 BDS Step9 0x6A BDS Step10 0x6B BDS Step11 0x6C BDS Step12 0x6D 0x6E 0x6F BDS Step13 BDS Step14 BDS return to DXE core (should not get here) continued 73

Section	Page
Intel® Desktop Board D2550DC2 Technical Product Specification	1
Revision History	2
Board Identification Information	3
Errata	3
Preface	5
Contents	7
1 Product Description	11
1.1 Overview	11
1.1.1 Feature Summary	11
1.1.2 Board Layout	13
1.1.3 Block Diagram	15
1.2 Online Support	16
1.3 Processor	16
1.3.1 Intel® D2550 Graphics Subsystem	17
1.4 System Memory	18
1.5 Intel® NM10 Express Chipset	20
1.5.2 USB	21
1.5.3 SATA Support	21
1.6 Real-Time Clock Subsystem	22
1.7 Legacy I/O Controller	22
1.8 LAN Subsystem	23
1.8.1 LAN Subsystem Drivers	23
1.8.2 RJ-45 LAN Connector with Integrated LEDs	24
1.9 Audio Subsystem	25
1.9.1 Audio Subsystem Software	26
1.9.2 Audio Connectors and Headers	26
1.10 Hardware Management Subsystem	27
1.10.1 Hardware Monitoring	27
1.10.2 Thermal Monitoring	28
1.11 Power Management	29
1.11.1 ACPI	29
1.11.2 Hardware Support	32
2 Technical Reference	35
2.1 Memory Map	35
2.1.1 Addressable Memory	35
2.2 Connectors and Headers	38
2.2.1 Back Panel	39
2.2.2 Component-side Connectors and Headers	41
2.3 BIOS Configuration Jumper Block	50
2.4 Mechanical Considerations	52
2.4.1 Form Factor	52
2.5 Electrical Considerations	53
2.5.1 Fan Header Current Capability	53
2.5.2 Add-in Board Considerations	53
2.6 Thermal Considerations	53
2.6.1 Passive Heatsink Design in a Passive System Environment	55
2.7 Power Consumption	58
2.7.1 Minimum Load Configuration	58
2.7.2 Maximum Load Configuration	58
2.8 Reliability	59
2.9 Environmental	59
3 Overview of BIOS Features	61
3.1 Introduction	61
3.2 BIOS Flash Memory Organization	62
3.3 Resource Configuration	62
3.3.1 PCI* Autoconfiguration	62
3.4 System Management BIOS (SMBIOS)	63
3.5 Legacy USB Support	64
3.6 BIOS Updates	65
3.6.1 BIOS Recovery	65
3.6.2 Custom Splash Screen	66
3.7 Boot Options	66
3.7.1 Optical Drive Boot	66
3.7.2 Network Boot	66
3.7.3 Booting Without Attached Devices	67
3.7.4 Changing the Default Boot Device During POST	67
3.8 BIOS Security Features	68
4 Board Status and Error Messages	69
4.1 BIOS Beep Codes	69
4.2 Front-panel Power LED Blink Codes	70
4.3 BIOS Error Messages	70
4.4 Port 80h POST Codes	71
5 Regulatory Compliance and Battery Disposal Information	77
5.1 Regulatory Compliance	77
5.1.1 Safety Standards	77
5.1.2 European Union Declaration of Conformity Statement	78
5.1.3 Product Ecology Statements	79
5.1.4 EMC Regulations	81
5.1.5 ENERGY STAR* 5.0, e-Standby, and ErP Compliance	84
5.1.6 Regulatory Compliance Marks (Board Level)	85