Intel D945GCCR Product Specification - Page 18

Memory Configurations

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Intel Desktop Board D945GCCR Technical Product Specification 1.4.1 Memory Configurations The Intel 82945GC GMCH supports two types of memory organization: • Dual channel (Interleaved) mode. This mode offers the highest throughput for real world applications. Dual channel mode is enabled when the installed memory capacities of both DIMM channels are equal. Technology and device width can vary from one channel to the other but the installed memory capacity for each channel must be equal. If different speed DIMMs are used between channels, the slowest memory timing will be used. • Single channel (Asymmetric) mode. This mode is equivalent to single channel bandwidth operation for real world applications. This mode is used when only a single DIMM is installed or the memory capacities are unequal. Technology and device width can vary from one channel to the other. If different speed DIMMs are used between channels, the slowest memory timing will be used. Figure 3 illustrates the memory channel and DIMM configuration. Figure 3. Memory Channel and DIMM Configuration 18

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Intel Desktop Board D945GCCR Technical Product Specification
18
1.4.1
Memory Configurations
The Intel 82945GC GMCH supports two types of memory organization:
Dual channel (Interleaved) mode
.
This mode offers the highest throughput for
real world applications.
Dual channel mode is enabled when the installed memory
capacities of both DIMM channels are equal.
Technology and device width can vary
from one channel to the other but the installed memory capacity for each channel
must be equal.
If different speed DIMMs are used between channels, the slowest
memory timing will be used.
Single channel (Asymmetric) mode
.
This mode is equivalent to single channel
bandwidth operation for real world applications.
This mode is used when only a
single DIMM is installed or the memory capacities are unequal.
Technology and
device width can vary from one channel to the other.
If different speed DIMMs are
used between channels, the slowest memory timing will be used.
Figure 3 illustrates the memory channel and DIMM configuration.
Figure 3.
Memory Channel and DIMM Configuration